[PATCH] D136847: [RISCV][NFC] Mark rs1 in most memory instructions as memory operand.

[Jessica Clarke via Phabricator via llvm-commits]

jrtc27 added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfo.td:131
 
-def GPRMemZeroOffset : RegisterOperand<GPR> {
+class MemOperand<RegisterClass regClass>: RegisterOperand<regClass>{
+  let OperandType = "OPERAND_MEMORY";
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: needs a space before it (repeated multiple times below)


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D136847/new/

https://reviews.llvm.org/D136847