[PATCH] D138045: [TargetLowering][RISCV][ARM][AArch64][Mips] Reduce the number of AND mask constants used by BSWAP expansion.

[Craig Topper via Phabricator via llvm-commits]

craig.topper created this revision.
craig.topper added reviewers: RKSimon, spatel, reames.
Herald added subscribers: sunshaoce, VincentWu, StephenFan, vkmr, frasercrmck, evandro, luismarques, apazos, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, the_o, brucehoult, MartinMosbeck, rogfer01, atanasyan, edward-jones, zzheng, jrtc27, shiva0217, kito-cheng, niosHD, sabuasal, simoncook, johnrusso, rbar, asb, hiraditya, kristof.beyls, arichardson, sdardis.
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craig.topper requested review of this revision.
Herald added subscribers: pcwang-thead, eopXD, MaskRay.
Herald added a project: LLVM.

We can reuse constants if we use SRL followed by AND and AND followed by SHL.
Similar was done to bitreverse previously.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D138045

Files:
  llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
  llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-rev.ll
  llvm/test/CodeGen/ARM/load-combine-big-endian.ll
  llvm/test/CodeGen/ARM/load-combine.ll
  llvm/test/CodeGen/Mips/bswap.ll
  llvm/test/CodeGen/RISCV/bswap-bitreverse.ll
  llvm/test/CodeGen/RISCV/rv32zbb.ll
  llvm/test/CodeGen/RISCV/rv64zbb.ll
  llvm/test/CodeGen/RISCV/rvv/bitreverse-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/bswap-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bswap.ll

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