[PATCH] D138043: [RISCV] Remove SExtWRemovalCands set from RISCVSExtWRemoval.

[Craig Topper via Phabricator via llvm-commits]

craig.topper created this revision.
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After D137970 <https://reviews.llvm.org/D137970>, we do the fixable instruction conversion in place
so we don't need to worry about iterator invalidation. This lets
us to conversion and updates in a single loop.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D138043

Files:
  llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp


Index: llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp
+++ llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp
@@ -497,10 +497,8 @@
   if (!ST.is64Bit())
     return false;
 
-  SmallPtrSet<MachineInstr *, 4> SExtWRemovalCands;
+  bool MadeChange = false;
 
-  // Replacing instructions invalidates the MI iterator
-  // we collect the candidates, then iterate over them separately.
   for (MachineBasicBlock &MBB : MF) {
     for (auto I = MBB.begin(), IE = MBB.end(); I != IE;) {
       MachineInstr *MI = &*I++;
@@ -514,38 +512,33 @@
       if (!SrcReg.isVirtual())
         continue;
 
-      SExtWRemovalCands.insert(MI);
-    }
-  }
+      SmallPtrSet<MachineInstr *, 4> FixableDef;
+      MachineInstr &SrcMI = *MRI.getVRegDef(SrcReg);
 
-  bool MadeChange = false;
-  for (auto *MI : SExtWRemovalCands) {
-    SmallPtrSet<MachineInstr *, 4> FixableDef;
-    Register SrcReg = MI->getOperand(1).getReg();
-    MachineInstr &SrcMI = *MRI.getVRegDef(SrcReg);
-
-    // If all definitions reaching MI sign-extend their output,
-    // then sext.w is redundant
-    if (!isSignExtendedW(SrcMI, MRI, FixableDef))
-      continue;
+      // If all definitions reaching MI sign-extend their output,
+      // then sext.w is redundant
+      if (!isSignExtendedW(SrcMI, MRI, FixableDef))
+        continue;
 
-    Register DstReg = MI->getOperand(0).getReg();
-    if (!MRI.constrainRegClass(SrcReg, MRI.getRegClass(DstReg)))
-      continue;
-    // Convert Fixable instructions to their W versions.
-    for (MachineInstr *Fixable : FixableDef) {
-      LLVM_DEBUG(dbgs() << "Replacing " << *Fixable);
-      Fixable->setDesc(TII.get(getWOp(Fixable->getOpcode())));
-      LLVM_DEBUG(dbgs() << "     with " << *Fixable);
-      ++NumTransformedToWInstrs;
-    }
+      Register DstReg = MI->getOperand(0).getReg();
+      if (!MRI.constrainRegClass(SrcReg, MRI.getRegClass(DstReg)))
+        continue;
 
-    LLVM_DEBUG(dbgs() << "Removing redundant sign-extension\n");
-    MRI.replaceRegWith(DstReg, SrcReg);
-    MRI.clearKillFlags(SrcReg);
-    MI->eraseFromParent();
-    ++NumRemovedSExtW;
-    MadeChange = true;
+      // Convert Fixable instructions to their W versions.
+      for (MachineInstr *Fixable : FixableDef) {
+        LLVM_DEBUG(dbgs() << "Replacing " << *Fixable);
+        Fixable->setDesc(TII.get(getWOp(Fixable->getOpcode())));
+        LLVM_DEBUG(dbgs() << "     with " << *Fixable);
+        ++NumTransformedToWInstrs;
+      }
+
+      LLVM_DEBUG(dbgs() << "Removing redundant sign-extension\n");
+      MRI.replaceRegWith(DstReg, SrcReg);
+      MRI.clearKillFlags(SrcReg);
+      MI->eraseFromParent();
+      ++NumRemovedSExtW;
+      MadeChange = true;
+    }
   }
 
   return MadeChange;


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