[PATCH] D137717: [AArch64][SVE] Fix bad PTEST(X, X) optimization
Cullen Rhodes via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Nov 15 03:59:55 PST 2022
This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGa290668ec547: [AArch64][SVE] Fix bad PTEST(X, X) optimization (authored by c-rhodes).
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D137717/new/
https://reviews.llvm.org/D137717
Files:
llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
llvm/test/CodeGen/AArch64/sve-ptest-removal-cmple.ll
llvm/test/CodeGen/AArch64/sve-ptest-removal-whilegt.mir
Index: llvm/test/CodeGen/AArch64/sve-ptest-removal-whilegt.mir
===================================================================
--- llvm/test/CodeGen/AArch64/sve-ptest-removal-whilegt.mir
+++ llvm/test/CodeGen/AArch64/sve-ptest-removal-whilegt.mir
@@ -462,7 +462,7 @@
liveins: $w0, $w1
; CHECK-LABEL: name: whilegt_b8_s32_ptest_with_matching_operands
- ; CHECK-NOT: PTEST
+ ; CHECK: PTEST
%1:gpr32 = COPY $w1
%0:gpr32 = COPY $w0
%2:ppr = WHILEGT_PWW_B %0, %1, implicit-def dead $nzcv
Index: llvm/test/CodeGen/AArch64/sve-ptest-removal-cmple.ll
===================================================================
--- llvm/test/CodeGen/AArch64/sve-ptest-removal-cmple.ll
+++ llvm/test/CodeGen/AArch64/sve-ptest-removal-cmple.ll
@@ -192,6 +192,7 @@
; CHECK-LABEL: cmp8_ptest_first_xx:
; CHECK: // %bb.0:
; CHECK-NEXT: cmpge p0.b, p0/z, z0.b, z1.b
+; CHECK-NEXT: ptest p0, p0.b
; CHECK-NEXT: cset w0, mi
; CHECK-NEXT: ret
%1 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.cmpge.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b)
@@ -207,6 +208,7 @@
; CHECK-LABEL: cmp8_ptest_last_xx:
; CHECK: // %bb.0:
; CHECK-NEXT: cmpge p0.b, p0/z, z0.b, z1.b
+; CHECK-NEXT: ptest p0, p0.b
; CHECK-NEXT: cset w0, lo
; CHECK-NEXT: ret
%1 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.cmpge.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b)
@@ -221,6 +223,7 @@
; CHECK-LABEL: cmp8_ptest_any_xx:
; CHECK: // %bb.0:
; CHECK-NEXT: cmpge p0.b, p0/z, z0.b, z1.b
+; CHECK-NEXT: ptest p0, p0.b
; CHECK-NEXT: cset w0, ne
; CHECK-NEXT: ret
%1 = tail call <vscale x 16 x i1> @llvm.aarch64.sve.cmpge.nxv16i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b)
@@ -236,6 +239,7 @@
; CHECK-LABEL: cmp32_ptest_first_xx:
; CHECK: // %bb.0:
; CHECK-NEXT: cmpge p0.s, p0/z, z0.s, z1.s
+; CHECK-NEXT: ptest p0, p0.b
; CHECK-NEXT: cset w0, mi
; CHECK-NEXT: ret
%1 = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
@@ -252,6 +256,7 @@
; CHECK-LABEL: cmp32_ptest_last_xx:
; CHECK: // %bb.0:
; CHECK-NEXT: cmpge p0.s, p0/z, z0.s, z1.s
+; CHECK-NEXT: ptest p0, p0.b
; CHECK-NEXT: cset w0, lo
; CHECK-NEXT: ret
%1 = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
@@ -267,6 +272,7 @@
; CHECK-LABEL: cmp32_ptest_any_xx:
; CHECK: // %bb.0:
; CHECK-NEXT: cmpge p0.s, p0/z, z0.s, z1.s
+; CHECK-NEXT: ptest p0, p0.b
; CHECK-NEXT: cset w0, ne
; CHECK-NEXT: ret
%1 = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
Index: llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
===================================================================
--- llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
+++ llvm/lib/Target/AArch64/AArch64InstrInfo.cpp
@@ -1318,11 +1318,6 @@
(Mask->getOperand(1).getImm() != 31))
return false;
- // Fallthough to simply remove the PTEST.
- } else if ((Mask == Pred) && (PredIsPTestLike || PredIsWhileLike)) {
- // For PTEST(PG, PG), PTEST is redundant when PG is the result of an
- // instruction that sets the flags as PTEST would.
-
// Fallthough to simply remove the PTEST.
} else if (PredIsPTestLike) {
// For PTEST(PG, PTEST_LIKE(PG, ...)), the PTEST is redundant since the
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