[PATCH] D138011: [PowerPC] Fix load-conversion pattern recognition in strictfp cases

[Qiu Chaofan via Phabricator via llvm-commits]

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Direct-move instructions are usually more efficient than load then store for conversion. But direct moves are not needed when the source register was just loaded from some address.

The pattern has already been recognized, but the source value of strict nodes are not the first (that's the chain), but the second. This patch fixes it and makes the peephole available to strict conversion operations.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D138011

Files:
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/test/CodeGen/PowerPC/fp-strict-conv.ll


Index: llvm/test/CodeGen/PowerPC/fp-strict-conv.ll
===================================================================
--- llvm/test/CodeGen/PowerPC/fp-strict-conv.ll
+++ llvm/test/CodeGen/PowerPC/fp-strict-conv.ll
@@ -501,8 +501,7 @@
 define double @load_i32_to_d(ptr %addr) #0 {
 ; CHECK-LABEL: load_i32_to_d:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    lwz r3, 0(r3)
-; CHECK-NEXT:    mtfprwa f0, r3
+; CHECK-NEXT:    lfiwax f0, 0, r3
 ; CHECK-NEXT:    xscvsxddp f1, f0
 ; CHECK-NEXT:    blr
 ;
@@ -520,8 +519,7 @@
 define double @load_i64_to_d(ptr %addr) #0 {
 ; CHECK-LABEL: load_i64_to_d:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    ld r3, 0(r3)
-; CHECK-NEXT:    mtfprd f0, r3
+; CHECK-NEXT:    lfd f0, 0(r3)
 ; CHECK-NEXT:    xscvsxddp f1, f0
 ; CHECK-NEXT:    blr
 ;
@@ -539,8 +537,7 @@
 define double @load_u32_to_d(ptr %addr) #0 {
 ; CHECK-LABEL: load_u32_to_d:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    lwz r3, 0(r3)
-; CHECK-NEXT:    mtfprwz f0, r3
+; CHECK-NEXT:    lfiwzx f0, 0, r3
 ; CHECK-NEXT:    xscvuxddp f1, f0
 ; CHECK-NEXT:    blr
 ;
@@ -558,8 +555,7 @@
 define double @load_u64_to_d(ptr %addr) #0 {
 ; CHECK-LABEL: load_u64_to_d:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    ld r3, 0(r3)
-; CHECK-NEXT:    mtfprd f0, r3
+; CHECK-NEXT:    lfd f0, 0(r3)
 ; CHECK-NEXT:    xscvuxddp f1, f0
 ; CHECK-NEXT:    blr
 ;
@@ -577,8 +573,7 @@
 define float @load_i32_to_f(ptr %addr) #0 {
 ; CHECK-LABEL: load_i32_to_f:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    lwz r3, 0(r3)
-; CHECK-NEXT:    mtfprwa f0, r3
+; CHECK-NEXT:    lfiwax f0, 0, r3
 ; CHECK-NEXT:    xscvsxdsp f1, f0
 ; CHECK-NEXT:    blr
 ;
@@ -596,8 +591,7 @@
 define float @load_i64_to_f(ptr %addr) #0 {
 ; CHECK-LABEL: load_i64_to_f:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    ld r3, 0(r3)
-; CHECK-NEXT:    mtfprd f0, r3
+; CHECK-NEXT:    lfd f0, 0(r3)
 ; CHECK-NEXT:    xscvsxdsp f1, f0
 ; CHECK-NEXT:    blr
 ;
@@ -615,8 +609,7 @@
 define float @load_u32_to_f(ptr %addr) #0 {
 ; CHECK-LABEL: load_u32_to_f:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    lwz r3, 0(r3)
-; CHECK-NEXT:    mtfprwz f0, r3
+; CHECK-NEXT:    lfiwzx f0, 0, r3
 ; CHECK-NEXT:    xscvuxdsp f1, f0
 ; CHECK-NEXT:    blr
 ;
@@ -634,8 +627,7 @@
 define float @load_u64_to_f(ptr %addr) #0 {
 ; CHECK-LABEL: load_u64_to_f:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    ld r3, 0(r3)
-; CHECK-NEXT:    mtfprd f0, r3
+; CHECK-NEXT:    lfd f0, 0(r3)
 ; CHECK-NEXT:    xscvuxdsp f1, f0
 ; CHECK-NEXT:    blr
 ;
Index: llvm/lib/Target/PowerPC/PPCISelLowering.cpp
===================================================================
--- llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -8334,7 +8334,7 @@
 /// prefer float load to int load plus direct move
 /// when there is no integer use of int load
 bool PPCTargetLowering::directMoveIsProfitable(const SDValue &Op) const {
-  SDNode *Origin = Op.getOperand(0).getNode();
+  SDNode *Origin = Op.getOperand(Op->isStrictFPOpcode() ? 1 : 0).getNode();
   if (Origin->getOpcode() != ISD::LOAD)
     return true;
 


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