[PATCH] D52369: [tblgen][disasm] Allow multiple encodings to disassemble to the same instruction

[James Y Knight via Phabricator via llvm-commits]

jyknight added a comment.

In D52369#3925972 <https://reviews.llvm.org/D52369#3925972>, @dsanders wrote:

> In D52369#3923428 <https://reviews.llvm.org/D52369#3923428>, @MaskRay wrote:
>
>> Is this feature (`AdditionalEncoding`) used by any downstream target? There is no in-tree user.
>>
>> (@jyknight)

Huh, despite doing a bunch of work recently in the encoder/decoder tablegen code, I never even noticed this feature existed before now. :)

> We use it extensively downstream to deal with variable length instructions

I'd note that we have many targets upstream which handle the "compressed instruction" idea just fine, without this feature. E.g. RISCV's "C" (compressed) instructions, ARM Thumb/Thumb2, CSKY 16-bit instrs, MicroMIPS, etc. In all cases, they define separate instructions for the "compressed" variant. AFAICT, none of them could actually use this feature even if it wasn't only restricted to disassembly -- they need to be able to express a different register class (since the compressed instruction allows fewer registers), or be able to tie input==output, because the compressed instruction has fewer register fields, or reduce the allowed range of the immediate, or ....

Probably it'd be better to have the downstream target also write multiple instruction definitions, using proper register classes/etc, instead of this hack.


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