[llvm] 65f9992 - [RISCV] Add PseudoCCMOVGPR to RISCVSExtWRemoval.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Mon Nov 14 13:41:32 PST 2022
Author: Craig Topper
Date: 2022-11-14T13:39:00-08:00
New Revision: 65f99928654869ea17aad00f2c5209f4a5f9d1dd
URL: https://github.com/llvm/llvm-project/commit/65f99928654869ea17aad00f2c5209f4a5f9d1dd
DIFF: https://github.com/llvm/llvm-project/commit/65f99928654869ea17aad00f2c5209f4a5f9d1dd.diff
LOG: [RISCV] Add PseudoCCMOVGPR to RISCVSExtWRemoval.
This instruction is a conditional move. It propagates sign bits
from its inputs.
Added:
Modified:
llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp b/llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp
index 1d57c8c725429..c040e01ad5cf4 100644
--- a/llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp
+++ b/llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp
@@ -211,6 +211,15 @@ static bool hasAllWUsers(const MachineInstr &OrigMI, MachineRegisterInfo &MRI) {
case RISCV::BINVI:
Worklist.push_back(UserMI);
break;
+
+ case RISCV::PseudoCCMOVGPR:
+ // Either operand 4 or operand 5 is returned by this instruction. If
+ // only the lower word of the result is used, then only the lower word
+ // of operand 4 and 5 is used.
+ if (OpIdx != 4 && OpIdx != 5)
+ return false;
+ Worklist.push_back(UserMI);
+ break;
}
}
}
@@ -396,19 +405,24 @@ static bool isSignExtendedW(MachineInstr &OrigMI, MachineRegisterInfo &MRI,
case RISCV::MAXU:
case RISCV::MIN:
case RISCV::MINU:
+ case RISCV::PseudoCCMOVGPR:
case RISCV::PHI: {
// If all incoming values are sign-extended, the output of AND, OR, XOR,
// MIN, MAX, or PHI is also sign-extended.
// The input registers for PHI are operand 1, 3, ...
+ // The input registers for PseudoCCMOVGPR are 4 and 5.
// The input registers for others are operand 1 and 2.
- unsigned E = 3, D = 1;
+ unsigned B = 1, E = 3, D = 1;
if (MI->getOpcode() == RISCV::PHI) {
E = MI->getNumOperands();
D = 2;
+ } else if (MI->getOpcode() == RISCV::PseudoCCMOVGPR) {
+ B = 4;
+ E = 6;
}
- for (unsigned I = 1; I != E; I += D) {
+ for (unsigned I = B; I != E; I += D) {
if (!MI->getOperand(I).isReg())
return false;
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