[llvm] ad68c66 - [DirectX backend] Fix build and test error caused by out of sync with upstream change.
Xiang Li via llvm-commits
llvm-commits at lists.llvm.org
Mon Nov 14 12:50:29 PST 2022
Author: Xiang Li
Date: 2022-11-14T12:50:23-08:00
New Revision: ad68c66a38ec9ec93f4c178c63dc6515b58dee66
URL: https://github.com/llvm/llvm-project/commit/ad68c66a38ec9ec93f4c178c63dc6515b58dee66
DIFF: https://github.com/llvm/llvm-project/commit/ad68c66a38ec9ec93f4c178c63dc6515b58dee66.diff
LOG: [DirectX backend] Fix build and test error caused by out of sync with upstream change.
Fix build and test error caused by
https://github.com/llvm/llvm-project/commit/a2620e00ffa232a406de3a1d8634beeda86956fd#
and
https://github.com/llvm/llvm-project/commit/304f1d59ca41872c094def3aee0a8689df6aa398
Reviewed By: beanz
Differential Revision: https://reviews.llvm.org/D137815
Added:
Modified:
llvm/lib/Target/DirectX/DXILPrepare.cpp
llvm/lib/Target/DirectX/DXILWriter/DXILBitcodeWriter.cpp
llvm/test/CodeGen/DirectX/strip-fn-attrs.ll
llvm/test/tools/dxil-dis/attribute-filter.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/DirectX/DXILPrepare.cpp b/llvm/lib/Target/DirectX/DXILPrepare.cpp
index e928ec57dc023..c044dd2fa592f 100644
--- a/llvm/lib/Target/DirectX/DXILPrepare.cpp
+++ b/llvm/lib/Target/DirectX/DXILPrepare.cpp
@@ -54,6 +54,7 @@ constexpr bool isValidForDXIL(Attribute::AttrKind Attr) {
Attribute::NonNull,
Attribute::Dereferenceable,
Attribute::DereferenceableOrNull,
+ Attribute::Memory,
Attribute::NoRedZone,
Attribute::NoReturn,
Attribute::NoUnwind,
@@ -61,7 +62,6 @@ constexpr bool isValidForDXIL(Attribute::AttrKind Attr) {
Attribute::OptimizeNone,
Attribute::ReadNone,
Attribute::ReadOnly,
- Attribute::ArgMemOnly,
Attribute::Returned,
Attribute::ReturnsTwice,
Attribute::SExt,
diff --git a/llvm/lib/Target/DirectX/DXILWriter/DXILBitcodeWriter.cpp b/llvm/lib/Target/DirectX/DXILWriter/DXILBitcodeWriter.cpp
index 09909a252ee9f..96c88ac49f1a6 100644
--- a/llvm/lib/Target/DirectX/DXILWriter/DXILBitcodeWriter.cpp
+++ b/llvm/lib/Target/DirectX/DXILWriter/DXILBitcodeWriter.cpp
@@ -49,6 +49,7 @@
#include "llvm/IR/ValueSymbolTable.h"
#include "llvm/Object/IRSymtab.h"
#include "llvm/Support/ErrorHandling.h"
+#include "llvm/Support/ModRef.h"
#include "llvm/Support/SHA1.h"
namespace llvm {
@@ -276,6 +277,13 @@ class DXILBitcodeWriter {
unsigned Abbrev) {
llvm_unreachable("DXIL cannot contain DIArgList Nodes");
}
+ void writeDIAssignID(const DIAssignID *N, SmallVectorImpl<uint64_t> &Record,
+ unsigned Abbrev) {
+ // DIAssignID is experimental feature to track variable location in IR..
+ // FIXME: translate DIAssignID to debug info DXIL supports.
+ // See https://github.com/llvm/llvm-project/issues/58989
+ llvm_unreachable("DXIL cannot contain DIAssignID Nodes");
+ }
void writeDIModule(const DIModule *N, SmallVectorImpl<uint64_t> &Record,
unsigned Abbrev);
void writeDITemplateTypeParameter(const DITemplateTypeParameter *N,
@@ -661,8 +669,6 @@ uint64_t DXILBitcodeWriter::getAttrKindEncoding(Attribute::AttrKind Kind) {
return bitc::ATTR_KIND_ALIGNMENT;
case Attribute::AlwaysInline:
return bitc::ATTR_KIND_ALWAYS_INLINE;
- case Attribute::ArgMemOnly:
- return bitc::ATTR_KIND_ARGMEMONLY;
case Attribute::Builtin:
return bitc::ATTR_KIND_BUILTIN;
case Attribute::ByVal:
@@ -929,12 +935,29 @@ void DXILBitcodeWriter::writeAttributeGroupTable() {
Record.push_back(0);
Record.push_back(Val);
} else if (Attr.isIntAttribute()) {
- uint64_t Val = getAttrKindEncoding(Attr.getKindAsEnum());
- assert(Val <= bitc::ATTR_KIND_ARGMEMONLY &&
- "DXIL does not support attributes above ATTR_KIND_ARGMEMONLY");
- Record.push_back(1);
- Record.push_back(Val);
- Record.push_back(Attr.getValueAsInt());
+ if (Attr.getKindAsEnum() == Attribute::AttrKind::Memory) {
+ MemoryEffects ME = Attr.getMemoryEffects();
+ if (ME.doesNotAccessMemory()) {
+ Record.push_back(0);
+ Record.push_back(bitc::ATTR_KIND_READ_NONE);
+ } else {
+ if (ME.onlyReadsMemory()) {
+ Record.push_back(0);
+ Record.push_back(bitc::ATTR_KIND_READ_ONLY);
+ }
+ if (ME.onlyAccessesArgPointees()) {
+ Record.push_back(0);
+ Record.push_back(bitc::ATTR_KIND_ARGMEMONLY);
+ }
+ }
+ } else {
+ uint64_t Val = getAttrKindEncoding(Attr.getKindAsEnum());
+ assert(Val <= bitc::ATTR_KIND_ARGMEMONLY &&
+ "DXIL does not support attributes above ATTR_KIND_ARGMEMONLY");
+ Record.push_back(1);
+ Record.push_back(Val);
+ Record.push_back(Attr.getValueAsInt());
+ }
} else {
StringRef Kind = Attr.getKindAsString();
StringRef Val = Attr.getValueAsString();
diff --git a/llvm/test/CodeGen/DirectX/strip-fn-attrs.ll b/llvm/test/CodeGen/DirectX/strip-fn-attrs.ll
index c1c7e2fab1d23..5c89ea5347feb 100644
--- a/llvm/test/CodeGen/DirectX/strip-fn-attrs.ll
+++ b/llvm/test/CodeGen/DirectX/strip-fn-attrs.ll
@@ -1,7 +1,7 @@
; RUN: llc %s --filetype=asm -o - | FileCheck %s
target triple = "dxil-unknown-shadermodel6.7-library"
-; CHECK: Function Attrs: nounwind readnone
+; CHECK: Function Attrs: nounwind memory(none)
; Function Attrs: norecurse nounwind readnone willreturn
define dso_local float @fma(float %0, float %1, float %2) local_unnamed_addr #0 {
%4 = fmul float %0, %1
@@ -9,11 +9,11 @@ define dso_local float @fma(float %0, float %1, float %2) local_unnamed_addr #0
ret float %5
}
-; CHECK: Function Attrs: nounwind readnone
+; CHECK: Function Attrs: nounwind memory(none)
; Function Attrs: nofree nosync nounwind readnone speculatable willreturn
declare void @llvm.dbg.value(metadata, metadata, metadata) #1
-; CHECK: attributes #0 = { nounwind readnone }
+; CHECK: attributes #0 = { nounwind memory(none) }
; CHECK-NOT attributes #
attributes #0 = { norecurse nounwind readnone willreturn }
diff --git a/llvm/test/tools/dxil-dis/attribute-filter.ll b/llvm/test/tools/dxil-dis/attribute-filter.ll
index 94a091c229e0c..432a5a1b71018 100644
--- a/llvm/test/tools/dxil-dis/attribute-filter.ll
+++ b/llvm/test/tools/dxil-dis/attribute-filter.ll
@@ -11,5 +11,16 @@ define float @fma(float %0, float %1, float %2) #0 {
ret float %5
}
+; CHECK: Function Attrs: readnone
+; Function Attrs: norecurse readnone willreturn
+define float @fma2(float %0, float %1, float %2) #1 {
+ %4 = fmul float %0, %1
+ %5 = fadd float %4, %2
+ ret float %5
+}
+
; CHECK: attributes #0 = { nounwind readnone "disable-tail-calls"="false" }
attributes #0 = { norecurse nounwind readnone willreturn "disable-tail-calls"="false" }
+
+; CHECK: attributes #1 = { readnone "disable-tail-calls"="false" }
+attributes #1 = { norecurse memory(none) willreturn "disable-tail-calls"="false" }
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