[PATCH] D137970: [RISCV] Transform fixable instruction in place in RISCVSExtWRemoval. NFC

[Craig Topper via Phabricator via llvm-commits]

craig.topper created this revision.
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Instead of creating a new instruction and copying operands, we can
use setDesc to convert in place.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D137970

Files:
  llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp


Index: llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp
+++ llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp
@@ -478,6 +478,7 @@
 
   MachineRegisterInfo &MRI = MF.getRegInfo();
   const RISCVSubtarget &ST = MF.getSubtarget<RISCVSubtarget>();
+  const RISCVInstrInfo &TII = *ST.getInstrInfo();
 
   if (!ST.is64Bit())
     return false;
@@ -517,22 +518,11 @@
     Register DstReg = MI->getOperand(0).getReg();
     if (!MRI.constrainRegClass(SrcReg, MRI.getRegClass(DstReg)))
       continue;
-    // Replace Fixable instructions with their W versions.
+    // Convert Fixable instructions to their W versions.
     for (MachineInstr *Fixable : FixableDef) {
-      MachineBasicBlock &MBB = *Fixable->getParent();
-      const DebugLoc &DL = Fixable->getDebugLoc();
-      unsigned Code = getWOp(Fixable->getOpcode());
-      MachineInstrBuilder Replacement =
-          BuildMI(MBB, Fixable, DL, ST.getInstrInfo()->get(Code));
-      for (auto Op : Fixable->operands())
-        Replacement.add(Op);
-      for (auto *Op : Fixable->memoperands())
-        Replacement.addMemOperand(Op);
-
       LLVM_DEBUG(dbgs() << "Replacing " << *Fixable);
-      LLVM_DEBUG(dbgs() << "     with " << *Replacement);
-
-      Fixable->eraseFromParent();
+      Fixable->setDesc(TII.get(getWOp(Fixable->getOpcode())));
+      LLVM_DEBUG(dbgs() << "     with " << *Fixable);
       ++NumTransformedToWInstrs;
     }
 


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