[PATCH] D137530: [RISCV] Splat scalar to be of length VL instead of 1 for reductions

[Wang Pengcheng via Phabricator via llvm-commits]

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Correct me if I am wrong, I think there is minmal microarchitecture
difference between vmv.s.x with vl==1 and v(f)mv.v.(ixf) with
vl==avl. So we can just splat scalar to be of length VL instead
of 1 to reduce context switch of vtype.

Two concerns:

- For LMUL>1, there are more than 1 registers that will be written

back. Should we limit this to cases where LMUL<=1?

- For floating-point cases, there are some regressions.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D137530

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int-vp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int.ll
  llvm/test/CodeGen/RISCV/rvv/fold-binary-reduce.ll
  llvm/test/CodeGen/RISCV/rvv/vreductions-fp-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/vreductions-fp-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vreductions-int-vp.ll
  llvm/test/CodeGen/RISCV/rvv/vreductions-int.ll

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