[PATCH] D137530: [RISCV] Splat scalar to be of length VL instead of 1 for reductions
Wang Pengcheng via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Sun Nov 6 23:34:21 PST 2022
pcwang-thead created this revision.
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Correct me if I am wrong, I think there is minmal microarchitecture
difference between vmv.s.x with vl==1 and v(f)mv.v.(ixf) with
vl==avl. So we can just splat scalar to be of length VL instead
of 1 to reduce context switch of vtype.
- For LMUL>1, there are more than 1 registers that will be written
back. Should we limit this to cases where LMUL<=1?
- For floating-point cases, there are some regressions.
rG LLVM Github Monorepo
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