[llvm] dca7b8e - AMDGPU: Add new test for target intrinsic aliasing metadata

[Matt Arsenault via llvm-commits]

Author: Matt Arsenault
Date: 2022-11-06T22:14:12-08:00
New Revision: dca7b8e23baa495d500dd1c4c1bbe9fc290530c4

URL: https://github.com/llvm/llvm-project/commit/dca7b8e23baa495d500dd1c4c1bbe9fc290530c4
DIFF: https://github.com/llvm/llvm-project/commit/dca7b8e23baa495d500dd1c4c1bbe9fc290530c4.diff

LOG: AMDGPU: Add new test for target intrinsic aliasing metadata

The intrinsic used for the test will soon be removed, so move
the test to use another one.

Replaces test added in fa4aac7335ac7ecabbb634d134bd4897783bf62b

Added: 
    llvm/test/CodeGen/AMDGPU/target-mem-intrinsic-metadata.ll

Modified: 
    llvm/test/CodeGen/AMDGPU/llvm.amdgcn.atomic.inc.ll

Removed: 
    


################################################################################
diff  --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.atomic.inc.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.atomic.inc.ll
index 1ad00dd639385..23792c6df0bc8 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.atomic.inc.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.atomic.inc.ll
@@ -1,7 +1,6 @@
 ; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,CI,CIVI %s
 ; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,VI,CIVI %s
 ; RUN: llc -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9 %s
-; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs -stop-before=machine-scheduler < %s | FileCheck -enable-var-scope -check-prefixes=MIR %s
 
 declare i32 @llvm.amdgcn.atomic.inc.i32.p1i32(i32 addrspace(1)* nocapture, i32, i32, i32, i1) #2
 declare i32 @llvm.amdgcn.atomic.inc.i32.p3i32(i32 addrspace(3)* nocapture, i32, i32, i32, i1) #2
@@ -19,18 +18,12 @@ declare i32 @llvm.amdgcn.workitem.id.x() #1
 
 ; GCN-DAG: v_mov_b32_e32 [[K:v[0-9]+]], 42
 ; GCN: ds_inc_rtn_u32 v{{[0-9]+}}, v{{[0-9]+}}, [[K]]
-; MIR-LABEL: @lds_atomic_inc_ret_i32
-; MIR: DS_INC_RTN_U32 {{.*}} :: (load store (s32) on %{{.*}}, !noalias !{{[0-9]+}}, addrspace 3)
 define amdgpu_kernel void @lds_atomic_inc_ret_i32(i32 addrspace(1)* %out, i32 addrspace(3)* %ptr) #0 {
-  %result = call i32 @llvm.amdgcn.atomic.inc.i32.p3i32(i32 addrspace(3)* %ptr, i32 42, i32 0, i32 0, i1 false), !noalias !0
+  %result = call i32 @llvm.amdgcn.atomic.inc.i32.p3i32(i32 addrspace(3)* %ptr, i32 42, i32 0, i32 0, i1 false)
   store i32 %result, i32 addrspace(1)* %out
   ret void
 }
 
-!0 = !{!1}
-!1 = distinct !{!1, !2}
-!2 = distinct !{!2}
-
 ; GCN-LABEL: {{^}}lds_atomic_inc_ret_i32_offset:
 ; CIVI-DAG: s_mov_b32 m0
 ; GFX9-NOT: m0

diff  --git a/llvm/test/CodeGen/AMDGPU/target-mem-intrinsic-metadata.ll b/llvm/test/CodeGen/AMDGPU/target-mem-intrinsic-metadata.ll
new file mode 100644
index 0000000000000..a68be9c78f728
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/target-mem-intrinsic-metadata.ll
@@ -0,0 +1,20 @@
+; RUN: llc -global-isel=0 -march=amdgcn -mcpu=bonaire -stop-before=machine-scheduler < %s | FileCheck -enable-var-scope -check-prefixes=MIR %s
+
+; Make sure !noalias metadata is passed through from target intrinsics
+
+; MIR-LABEL: name: ds_append_noalias
+; MIR: DS_APPEND {{.*}} :: (load store (s32) on %{{.*}}, !noalias !{{[0-9]+}}, addrspace 3)
+define amdgpu_kernel void @ds_append_noalias() {
+  %lds = load i32 addrspace(3)*, i32 addrspace(3)* addrspace(1)* null
+  %val = call i32 @llvm.amdgcn.ds.append.p3i32(i32 addrspace(3)* %lds, i1 false), !noalias !0
+  store i32 %val, i32 addrspace(1)* null, align 4
+  ret void
+}
+
+declare i32 @llvm.amdgcn.ds.append.p3i32(i32 addrspace(3)* nocapture, i1 immarg) #0
+
+attributes #0 = { argmemonly convergent nounwind willreturn }
+
+!0 = !{!1}
+!1 = distinct !{!1, !2}
+!2 = distinct !{!2}