[PATCH] D137504: [PowerPC] Implement 64-bit ELFv2 Calling Convention in TableGen (for integers/floats/vectors in registers)

[Amy Kwan via Phabricator via llvm-commits]

amyk created this revision.
amyk added reviewers: PowerPC, Kai, nemanjai.
amyk added projects: LLVM, PowerPC.
Herald added subscribers: steven.zhang, shchenz, kbarton, hiraditya.
Herald added a project: All.
amyk requested review of this revision.
Herald added a subscriber: llvm-commits.

This patch partially implements the parameter passing rules outlined in the ELFv2 ABI
within TableGen. Specifically, it implements the parameter assignment of integers, floats, and
vectors within registers - where the GPR numbering will be "skipped" depending on the ordering
of floats and vectors that appear within a parameter list.

As we begin to adopt GlobalISel to the PowerPC backend, there is a need for a TableGen definition 
that encapsulates the ELFv2 parameter passing rules. Thus, this patch also changes the default
calling convention that is returned within the `ccAssignFnForCall()` function used in our GlobalISel
implementation, and also adds some additional testing of the calling convention that is implemented.

Future patches that build on top of this initial TableGen definition will aim to add more of the
ABI complexities, including support for additional types and also in-memory arguments.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D137504

Files:
  llvm/lib/Target/PowerPC/PPCCallingConv.cpp
  llvm/lib/Target/PowerPC/PPCCallingConv.h
  llvm/lib/Target/PowerPC/PPCCallingConv.td
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/test/CodeGen/PowerPC/GlobalISel/irtranslator-args-lowering-fp128.ll
  llvm/test/CodeGen/PowerPC/GlobalISel/irtranslator-args-lowering-mixed-types.ll
  llvm/test/CodeGen/PowerPC/GlobalISel/irtranslator-args-lowering-scalar.ll
  llvm/test/CodeGen/PowerPC/GlobalISel/irtranslator-args-lowering-vectors.ll
  llvm/test/CodeGen/PowerPC/GlobalISel/irtranslator-args-lowering.ll

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