[llvm] a41cb8b - [SimpleLoopUnswitch] Forget block & loop dispos during trivial unswitch.

[Florian Hahn via llvm-commits]

Author: Florian Hahn
Date: 2022-11-05T16:56:06Z
New Revision: a41cb8bf58aec8d8bdc2134267d68267886ef9f4

URL: https://github.com/llvm/llvm-project/commit/a41cb8bf58aec8d8bdc2134267d68267886ef9f4
DIFF: https://github.com/llvm/llvm-project/commit/a41cb8bf58aec8d8bdc2134267d68267886ef9f4.diff

LOG: [SimpleLoopUnswitch] Forget block & loop dispos during trivial unswitch.

Unswitching adjusts the CFG in ways that may invalidate cached loop
dispositions. Clear all cached block and loop dispositions during
trivial unswitching. The same is already done for non-trivial
unswitching.

Fixes #58751.

Added: 
    

Modified: 
    llvm/lib/Transforms/Scalar/SimpleLoopUnswitch.cpp
    llvm/test/Transforms/SimpleLoopUnswitch/invalidate-block-and-loop-dispositions.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Transforms/Scalar/SimpleLoopUnswitch.cpp b/llvm/lib/Transforms/Scalar/SimpleLoopUnswitch.cpp
index de7e0500a97ca..a434394f2cdac 100644
--- a/llvm/lib/Transforms/Scalar/SimpleLoopUnswitch.cpp
+++ b/llvm/lib/Transforms/Scalar/SimpleLoopUnswitch.cpp
@@ -541,6 +541,7 @@ static bool unswitchTrivialBranch(Loop &L, BranchInst &BI, DominatorTree &DT,
     else
       // Forget the entire nest as this exits the entire nest.
       SE->forgetTopmostLoop(&L);
+    SE->forgetBlockAndLoopDispositions();
   }
 
   if (MSSAU && VerifyMemorySSA)

diff  --git a/llvm/test/Transforms/SimpleLoopUnswitch/invalidate-block-and-loop-dispositions.ll b/llvm/test/Transforms/SimpleLoopUnswitch/invalidate-block-and-loop-dispositions.ll
index c7ce403f808eb..fcef88667449f 100644
--- a/llvm/test/Transforms/SimpleLoopUnswitch/invalidate-block-and-loop-dispositions.ll
+++ b/llvm/test/Transforms/SimpleLoopUnswitch/invalidate-block-and-loop-dispositions.ll
@@ -110,3 +110,31 @@ inner:
 }
 
 declare i16 @bar()
+
+define void @pr58751(i16 %a, ptr %dst) {
+entry:
+  %c.1 = icmp eq i16 %a, 0
+  br label %outer.header
+
+outer.header:
+  %outer.iv = phi i16 [ %a, %entry ], [ %outer.iv.next, %outer.latch ]
+  br label %inner.header
+
+inner.header:
+  %inner.iv = phi i16 [ %outer.iv, %outer.header ], [ %inner.iv.next, %inner.latch ]
+  br i1 %c.1, label %outer.latch, label %inner.latch
+
+inner.latch:
+  %inner.iv.next = add nsw i16 %inner.iv, 1
+  store i16 %inner.iv.next, ptr %dst, align 1
+  %c.2 = icmp eq i16 %inner.iv.next, 0
+  br i1 %c.2, label %exit, label %inner.header
+
+outer.latch:
+  %outer.iv.next = add nsw i16 %outer.iv, 1
+  br label %outer.header
+
+exit:
+  ret void
+}
+