[llvm] d95dc5b - [X86] Replace unnecessary int2double overrides with a better WriteCvtI2PD def
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Sat Nov 5 04:28:02 PDT 2022
Author: Simon Pilgrim
Date: 2022-11-05T11:27:53Z
New Revision: d95dc5bce9dfea001423e22a37e150d0b782012d
URL: https://github.com/llvm/llvm-project/commit/d95dc5bce9dfea001423e22a37e150d0b782012d
DIFF: https://github.com/llvm/llvm-project/commit/d95dc5bce9dfea001423e22a37e150d0b782012d.diff
LOG: [X86] Replace unnecessary int2double overrides with a better WriteCvtI2PD def
Broadwell, Haswell and SkylakeClient were completely overriding the WriteCvtI2PD defs - we can remove those overrides entirely by replacing the unused WriteCvtI2PD values
There's plenty more of these in the scheduler models - I'm looking at improving warnings in llvm-tblgen to catch them all
Added:
Modified:
llvm/lib/Target/X86/X86SchedBroadwell.td
llvm/lib/Target/X86/X86SchedHaswell.td
llvm/lib/Target/X86/X86SchedSkylakeClient.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/X86/X86SchedBroadwell.td b/llvm/lib/Target/X86/X86SchedBroadwell.td
index 35a776941485a..3c6a6a5170d99 100644
--- a/llvm/lib/Target/X86/X86SchedBroadwell.td
+++ b/llvm/lib/Target/X86/X86SchedBroadwell.td
@@ -371,8 +371,8 @@ defm : BWWriteResPair<WriteCvtI2PS, [BWPort1], 4>;
defm : BWWriteResPair<WriteCvtI2PSY, [BWPort1], 4>;
defm : X86WriteResPairUnsupported<WriteCvtI2PSZ>;
defm : BWWriteResPair<WriteCvtI2SD, [BWPort1], 4>;
-defm : BWWriteResPair<WriteCvtI2PD, [BWPort1], 4>;
-defm : BWWriteResPair<WriteCvtI2PDY, [BWPort1], 4>;
+defm : BWWriteResPair<WriteCvtI2PD, [BWPort1,BWPort5], 4, [1,1], 2, 5>;
+defm : BWWriteResPair<WriteCvtI2PDY, [BWPort1,BWPort5], 6, [1,1], 2, 5>;
defm : X86WriteResPairUnsupported<WriteCvtI2PDZ>;
defm : BWWriteResPair<WriteCvtSS2SD, [BWPort1], 3>;
@@ -877,10 +877,8 @@ def BWWriteResGroup42 : SchedWriteRes<[BWPort1,BWPort5]> {
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[BWWriteResGroup42], (instrs MMX_CVTPI2PDrr)>;
def: InstRW<[BWWriteResGroup42], (instregex "MMX_CVT(T?)PD2PIrr",
"MMX_CVT(T?)PS2PIrr",
- "(V?)CVTDQ2PDrr",
"(V?)CVTPD2PSrr",
"(V?)CVTSD2SSrr",
"(V?)CVTSI642SDrr",
@@ -1005,8 +1003,7 @@ def BWWriteResGroup60 : SchedWriteRes<[BWPort1,BWPort5]> {
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[BWWriteResGroup60], (instrs VCVTDQ2PDYrr,
- VCVTPD2PSYrr,
+def: InstRW<[BWWriteResGroup60], (instrs VCVTPD2PSYrr,
VCVTPD2DQYrr,
VCVTTPD2DQYrr)>;
@@ -1250,10 +1247,8 @@ def BWWriteResGroup107 : SchedWriteRes<[BWPort1,BWPort5,BWPort23]> {
}
def: InstRW<[BWWriteResGroup107], (instrs CVTPD2PSrm,
CVTPD2DQrm,
- CVTTPD2DQrm,
- MMX_CVTPI2PDrm)>;
+ CVTTPD2DQrm)>;
def: InstRW<[BWWriteResGroup107], (instregex "MMX_CVT(T?)PD2PIrm",
- "(V?)CVTDQ2PDrm",
"(V?)CVTSD2SSrm")>;
def BWWriteResGroup108 : SchedWriteRes<[BWPort5,BWPort23,BWPort015]> {
@@ -1315,13 +1310,6 @@ def BWWriteResGroup123 : SchedWriteRes<[BWPort0,BWPort23]> {
def: InstRW<[BWWriteResGroup123], (instregex "MUL_F(32|64)m")>;
def: InstRW<[BWWriteResGroup123], (instrs VPCMPGTQYrm)>;
-def BWWriteResGroup128 : SchedWriteRes<[BWPort1,BWPort5,BWPort23]> {
- let Latency = 11;
- let NumMicroOps = 3;
- let ResourceCycles = [1,1,1];
-}
-def: InstRW<[BWWriteResGroup128], (instrs VCVTDQ2PDYrm)>;
-
def BWWriteResGroup131 : SchedWriteRes<[BWPort1,BWPort06,BWPort0156]> {
let Latency = 11;
let NumMicroOps = 7;
diff --git a/llvm/lib/Target/X86/X86SchedHaswell.td b/llvm/lib/Target/X86/X86SchedHaswell.td
index d1d385bfaf49f..b759423a14b25 100644
--- a/llvm/lib/Target/X86/X86SchedHaswell.td
+++ b/llvm/lib/Target/X86/X86SchedHaswell.td
@@ -365,9 +365,9 @@ defm : HWWriteResPair<WriteCvtPS2IY, [HWPort1], 3>;
defm : HWWriteResPair<WriteCvtPS2IZ, [HWPort1], 3>; // Unsupported = 1
defm : HWWriteResPair<WriteCvtI2SD, [HWPort1], 4>;
-defm : HWWriteResPair<WriteCvtI2PD, [HWPort1], 4>;
-defm : HWWriteResPair<WriteCvtI2PDY, [HWPort1], 4>;
-defm : HWWriteResPair<WriteCvtI2PDZ, [HWPort1], 4>; // Unsupported = 1
+defm : HWWriteResPair<WriteCvtI2PD, [HWPort1,HWPort5], 4, [1,1], 2, 6>;
+defm : HWWriteResPair<WriteCvtI2PDY, [HWPort1,HWPort5], 6, [1,1], 2, 6>;
+defm : HWWriteResPair<WriteCvtI2PDZ, [HWPort1,HWPort5], 6, [1,1], 2, 6>; // Unsupported = 1
defm : HWWriteResPair<WriteCvtI2SS, [HWPort1], 4>;
defm : HWWriteResPair<WriteCvtI2PS, [HWPort1], 4>;
defm : HWWriteResPair<WriteCvtI2PSY, [HWPort1], 4>;
@@ -1388,13 +1388,11 @@ def HWWriteResGroup73 : SchedWriteRes<[HWPort1,HWPort5]> {
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[HWWriteResGroup73], (instrs MMX_CVTPI2PDrr,
- MMX_CVTPD2PIrr,
+def: InstRW<[HWWriteResGroup73], (instrs MMX_CVTPD2PIrr,
MMX_CVTPS2PIrr,
MMX_CVTTPD2PIrr,
MMX_CVTTPS2PIrr)>;
-def: InstRW<[HWWriteResGroup73], (instregex "(V?)CVTDQ2PDrr",
- "(V?)CVTPD2PSrr",
+def: InstRW<[HWWriteResGroup73], (instregex "(V?)CVTPD2PSrr",
"(V?)CVTSD2SSrr",
"(V?)CVTSI(64)?2SDrr",
"(V?)CVTSI2SSrr",
@@ -1434,9 +1432,7 @@ def: InstRW<[HWWriteResGroup78], (instrs CVTPD2PSrm,
CVTPD2DQrm,
CVTTPD2DQrm,
MMX_CVTPD2PIrm,
- MMX_CVTTPD2PIrm,
- CVTDQ2PDrm,
- VCVTDQ2PDrm)>;
+ MMX_CVTTPD2PIrm)>;
def HWWriteResGroup78_1 : SchedWriteRes<[HWPort1,HWPort5,HWPort23]> {
let Latency = 9;
@@ -1552,8 +1548,7 @@ def HWWriteResGroup102 : SchedWriteRes<[HWPort1,HWPort5]> {
let NumMicroOps = 2;
let ResourceCycles = [1,1];
}
-def: InstRW<[HWWriteResGroup102], (instrs VCVTDQ2PDYrr,
- VCVTPD2PSYrr,
+def: InstRW<[HWWriteResGroup102], (instrs VCVTPD2PSYrr,
VCVTPD2DQYrr,
VCVTTPD2DQYrr)>;
@@ -1564,13 +1559,6 @@ def HWWriteResGroup103 : SchedWriteRes<[HWPort1,HWPort23]> {
}
def: InstRW<[HWWriteResGroup103], (instregex "(ADD|SUB|SUBR)_FI(16|32)m")>;
-def HWWriteResGroup104 : SchedWriteRes<[HWPort1,HWPort5,HWPort23]> {
- let Latency = 12;
- let NumMicroOps = 3;
- let ResourceCycles = [1,1,1];
-}
-def: InstRW<[HWWriteResGroup104], (instrs VCVTDQ2PDYrm)>;
-
def HWWriteResGroup107 : SchedWriteRes<[HWPort1,HWPort6,HWPort06,HWPort0156]> {
let Latency = 6;
let NumMicroOps = 4;
diff --git a/llvm/lib/Target/X86/X86SchedSkylakeClient.td b/llvm/lib/Target/X86/X86SchedSkylakeClient.td
index ba245bb6358b5..ffc5d9730d63a 100644
--- a/llvm/lib/Target/X86/X86SchedSkylakeClient.td
+++ b/llvm/lib/Target/X86/X86SchedSkylakeClient.td
@@ -456,8 +456,8 @@ defm : SKLWriteResPair<WriteCvtI2PS, [SKLPort1], 4>;
defm : SKLWriteResPair<WriteCvtI2PSY, [SKLPort1], 4>;
defm : X86WriteResPairUnsupported<WriteCvtI2PSZ>;
defm : SKLWriteResPair<WriteCvtI2SD, [SKLPort1], 4>;
-defm : SKLWriteResPair<WriteCvtI2PD, [SKLPort1], 4>;
-defm : SKLWriteResPair<WriteCvtI2PDY, [SKLPort1], 4>;
+defm : SKLWriteResPair<WriteCvtI2PD, [SKLPort0,SKLPort5], 5, [1,1], 2, 6>;
+defm : SKLWriteResPair<WriteCvtI2PDY, [SKLPort0,SKLPort5], 7, [1,1], 2, 6>;
defm : X86WriteResPairUnsupported<WriteCvtI2PDZ>;
defm : SKLWriteResPair<WriteCvtSS2SD, [SKLPort1], 3>;
@@ -936,15 +936,6 @@ def SKLWriteResGroup58 : SchedWriteRes<[SKLPort23]> {
def: InstRW<[SKLWriteResGroup58], (instregex "MOVSX(16|32|64)rm(8|16|32)",
"MOVZX(16|32|64)rm(8|16)")>;
-def SKLWriteResGroup59 : SchedWriteRes<[SKLPort0,SKLPort5]> {
- let Latency = 5;
- let NumMicroOps = 2;
- let ResourceCycles = [1,1];
-}
-def: InstRW<[SKLWriteResGroup59], (instrs MMX_CVTPI2PDrr,
- CVTDQ2PDrr,
- VCVTDQ2PDrr)>;
-
def SKLWriteResGroup60 : SchedWriteRes<[SKLPort5,SKLPort015]> {
let Latency = 5;
let NumMicroOps = 2;
@@ -1113,13 +1104,6 @@ def: InstRW<[SKLWriteResGroup85], (instrs VBROADCASTF128,
VPBROADCASTDYrm,
VPBROADCASTQYrm)>;
-def SKLWriteResGroup86 : SchedWriteRes<[SKLPort0,SKLPort5]> {
- let Latency = 7;
- let NumMicroOps = 2;
- let ResourceCycles = [1,1];
-}
-def: InstRW<[SKLWriteResGroup86], (instrs VCVTDQ2PDYrr)>;
-
def SKLWriteResGroup88 : SchedWriteRes<[SKLPort5,SKLPort23]> {
let Latency = 6;
let NumMicroOps = 2;
@@ -1408,13 +1392,6 @@ def SKLWriteResGroup149 : SchedWriteRes<[SKLPort5,SKLPort23]> {
}
def: InstRW<[SKLWriteResGroup149], (instregex "FICOM(P?)(16|32)m")>;
-def SKLWriteResGroup150 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> {
- let Latency = 11;
- let NumMicroOps = 3;
- let ResourceCycles = [1,1,1];
-}
-def: InstRW<[SKLWriteResGroup150], (instregex "(V?)CVTDQ2PDrm")>;
-
def SKLWriteResGroup151 : SchedWriteRes<[SKLPort0,SKLPort23,SKLPort01]> {
let Latency = 11;
let NumMicroOps = 3;
@@ -1472,13 +1449,6 @@ def SKLWriteResGroup162 : SchedWriteRes<[SKLPort5,SKLPort23]> {
}
def: InstRW<[SKLWriteResGroup162], (instregex "(ADD|SUB|SUBR)_FI(16|32)m")>;
-def SKLWriteResGroup163 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> {
- let Latency = 13;
- let NumMicroOps = 3;
- let ResourceCycles = [1,1,1];
-}
-def: InstRW<[SKLWriteResGroup163], (instrs VCVTDQ2PDYrm)>;
-
def SKLWriteResGroup169 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> {
let Latency = 14;
let NumMicroOps = 3;
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