[PATCH] D137481: [TargetLowering] Do not shrink shift amount in ShrinkDemandedOp

[chenglin.bi via Phabricator via llvm-commits]

bcl5980 created this revision.
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Shift amout is determined by TLI.getShiftAmountTy. We can't truncate it.


https://reviews.llvm.org/D137481

Files:
  llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp


Index: llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
===================================================================
--- llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -582,11 +582,16 @@
     EVT SmallVT = EVT::getIntegerVT(*DAG.getContext(), SmallVTBits);
     if (TLI.isTruncateFree(Op.getValueType(), SmallVT) &&
         TLI.isZExtFree(SmallVT, Op.getValueType())) {
+      SDValue RHS = Op.getOperand(1);
+      // Shift amout type is determined by TLI.getShiftAmountTy,
+      // we can't truncate here because it will cause type mismatch.
+      if (Op.getOpcode() != ISD::SHL && Op.getOpcode() != ISD::SRL &&
+          Op.getOpcode() != ISD::SRA)
+        RHS = DAG.getNode(ISD::TRUNCATE, dl, SmallVT, RHS);
       // We found a type with free casts.
       SDValue X = DAG.getNode(
           Op.getOpcode(), dl, SmallVT,
-          DAG.getNode(ISD::TRUNCATE, dl, SmallVT, Op.getOperand(0)),
-          DAG.getNode(ISD::TRUNCATE, dl, SmallVT, Op.getOperand(1)));
+          DAG.getNode(ISD::TRUNCATE, dl, SmallVT, Op.getOperand(0)), RHS);
       assert(DemandedSize <= SmallVTBits && "Narrowed below demanded bits?");
       SDValue Z = DAG.getNode(ISD::ANY_EXTEND, dl, Op.getValueType(), X);
       return TLO.CombineTo(Op, Z);


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