[PATCH] D137452: [RISCV] Support BSET/BCLR/BINV in isAllUsesReadW.

[Craig Topper via Phabricator via llvm-commits]

craig.topper created this revision.
craig.topper added reviewers: mohammed-nurulhoque, reames, kito-cheng, frasercrmck, asb, luismarques.
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These instructions set, clear, or invert a single bit. If their
users don't use the upper 32 bits, they don't use the upper 32 bits
of their input.

Additionally the second operand BSET/BCLR/BINV is a shift amount
which only uses 6 bits of the source.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D137452

Files:
  llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp


Index: llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp
+++ llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp
@@ -140,6 +140,9 @@
         break;
 
       case RISCV::SLL:
+      case RISCV::BSET:
+      case RISCV::BCLR:
+      case RISCV::BINV:
         // Operand 2 is the shift amount which uses 6 bits.
         if (OpIdx == 2)
           break;
@@ -200,6 +203,9 @@
       case RISCV::SH2ADD:
       case RISCV::SH3ADD:
       case RISCV::XNOR:
+      case RISCV::BSETI:
+      case RISCV::BCLRI:
+      case RISCV::BINVI:
         Worklist.push_back(UserMI);
         break;
       }


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