[PATCH] D137412: [AArch64][SVE2] Add the SVE2.1 add quadword reduction instruction

[Paul Walker via Phabricator via llvm-commits]

paulwalker-arm added inline comments.


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Comment at: llvm/lib/Target/AArch64/SVEInstrFormats.td:9232-9235
+class sve2p1_add_reduction_q<bits<2> sz, bits<2> opc, string mnemonic,
+                             RegisterOperand zpr_ty, string vec_sfx>
+    : I<(outs V128:$Vd), (ins PPR3bAny:$Pg, zpr_ty:$Zn),
+        mnemonic, "\t$Vd." # vec_sfx # ", $Pg, $Zn",
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As per my comment on D137411, can you use a similar class hierarchy as use by the normal reduction intrinsics?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D137412/new/

https://reviews.llvm.org/D137412