[PATCH] D137426: [RISCV][Codegen] Account for LMUL in Vector floating-point instructions

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVScheduleV.td:16
+defvar SchedMxListFW = ["UpperBound", "MF4", "MF2", "M1", "M2", "M4"];
+defvar SchedMxListFPW = ["UpperBound", "MF4", "MF2", "M1", "M2", "M4", "M8"];
 
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It seems like a bug that we need both of these. I'm going to investigate.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D137426/new/

https://reviews.llvm.org/D137426