[PATCH] D137429: [RISCV][CodeGen] Account for LMUL for Vector Integer load store instructions

[Michael Maitland via Phabricator via llvm-commits]

michaelmaitland created this revision.
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It is likley that subtargets act differently for a vector load store instructions based on the LMUL.
This patch creates seperate SchedRead, SchedWrite, WriteRes, ReadAdvance for each relevant LMUL.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D137429

Files:
  llvm/lib/Target/RISCV/RISCVInstrInfoV.td
  llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
  llvm/lib/Target/RISCV/RISCVScheduleV.td

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