[PATCH] D136525: [M68k] Add codegen pattern for atomic load / store

[Sheng via Phabricator via llvm-commits]

0x59616e marked 4 inline comments as done.
0x59616e added inline comments.


================
Comment at: llvm/lib/Target/M68k/M68kInstrAtomics.td:10
+// FIXME: This is only supported on MC68020 and later.
+class MxCASOp<bits<2> size_encoding, MxType type>
+    : MxInst<(outs type.ROp:$out),
----------------
myhsu wrote:
> 0x59616e wrote:
> > RKSimon wrote:
> > > Wrap this inside FeatureISA20 ?
> > Is there any example I can refer to ?
> you can use `let Predicates = [IsM68020] in { ...` to wrap both the instruction definitions and the patterns (the predicates won't be honored if you only wrap the instruction definitions, since we're using custom patterns). Though I just realized that the `IsM680X0` predicates defined in M68kInstrInfo.td are wrong. I will fix that shortly.
Something like D137425 ?


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D136525/new/

https://reviews.llvm.org/D136525