[PATCH] D136142: [AArch64]SME2 MOV Instructions
Caroline via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Fri Nov 4 04:33:00 PDT 2022
CarolineConcatto added inline comments.
================
Comment at: llvm/lib/Target/AArch64/SMEInstrFormats.td:2671
+
+multiclass sme2_mova_vec_to_tile_or_array_aliases<int prefer, Instruction inst,
+ RegisterOperand tile_or_array_ty,
----------------
paulwalker-arm wrote:
> To be honest I don't see any value to this class, especially as it only contains a single `InstAlias`. I think the aliases will be more readable if just emitted directly.
We created precendent for that when we created for sme1
multiclass sme_vector_to_tile_aliases<
I try to remove the alias class, but one class like this:
```
defm : sme2_mova_vec_to_tile_or_array_aliases<1, !cast<Instruction>(NAME # _B),
!if(v, TileVectorOpV8,
TileVectorOpH8),
MatrixIndexGPR32Op12_15,
uimm3s2range, ZZ_b_mul_r,
"mov">;
```
Would become 2, one for Horizontal and another for Vertical:
```
def : InstAlias<mnemonic # "\t$ZAd[$Rs, $imm], $Zn",
(!cast<Instruction>(NAME # _B) TileVector8H:$ZAd, rv_ty:$Rs, index_ty:$imm, ZZ_b_mul_r:$Zn), 1>;
def : InstAlias<mnemonic # "\t$ZAd[$Rs, $imm], $Zn",
(!cast<Instruction>(NAME # _B) TileVector8V:$ZAd, rv_ty:$Rs, index_ty:$imm, ZZ_b_mul_r:$Zn), 1>;
```
We will have to duplicate the number of alias.
And I cannot pass the types (TileVector8H/TileVector8V, TileVector16H/TileVector16V/...)in the previous class :
```
multiclass sme2_mova_vec_to_tile_vg2_multi<string mnemonic>{
defm _H : sme2_mova_vec_to_tile_vg2_multi_base<0b0, mnemonic>;
defm _V : sme2_mova_vec_to_tile_vg2_multi_base<0b1, mnemonic>;
}
```
Because it depends on the size.
Unless you know some tricks in tablegen to solve that problem.
Repository:
rG LLVM Github Monorepo
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https://reviews.llvm.org/D136142/new/
https://reviews.llvm.org/D136142
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