[PATCH] D136091: [AArch64] SME2 multi-vec unpack, ZIP, frint for two and four registers

[Paul Walker via Phabricator via llvm-commits]

paulwalker-arm accepted this revision.
paulwalker-arm added inline comments.
This revision is now accepted and ready to land.


================
Comment at: llvm/lib/Target/AArch64/SMEInstrFormats.td:1788
+multiclass sme2_fp_cvt_vg2_multi<string mnemonic, bits<5> op> {
+  def _S : sme2_frint_cvt_vg2_multi<0b00, op, ZZ_s_mul_r, ZZ_s_mul_r, mnemonic>;
+}
----------------
This should be `NAME` because you're already suffixing the instructions with `_StoS`.


================
Comment at: llvm/lib/Target/AArch64/SMEInstrFormats.td:1851-1852
+  let Inst{22}    = op{3};
+  let Inst{21}    = 0b1;
+  let Inst{20-18} = 0b000;
+  let Inst{17-16} = op{2-1};
----------------
`Inst{21-18} = 0b1000;`


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D136091/new/

https://reviews.llvm.org/D136091