[llvm] ef0d689 - [SelectionDAGBuilder] use bitcast instead of AnyExtOrTrunc if copy parts from an int vector to a float vector to fix issue #58615

[Peter Rong via llvm-commits]

Author: Henry Yu
Date: 2022-11-03T15:35:13-07:00
New Revision: ef0d689e8be2ac22b2e2da477217c761354c0ff9

URL: https://github.com/llvm/llvm-project/commit/ef0d689e8be2ac22b2e2da477217c761354c0ff9
DIFF: https://github.com/llvm/llvm-project/commit/ef0d689e8be2ac22b2e2da477217c761354c0ff9.diff

LOG: [SelectionDAGBuilder] use bitcast instead of AnyExtOrTrunc if copy parts from an int vector to a float vector to fix issue #58615

The getCopyFromPartsVector doesn't work correctly when PartEVT and ValueVT have both different element type and different size.

This patch
1) removes the part of a comment that contains the incorrect assumption that element type are the same
2) use bitcast when copy parts of int vector to a float vector after the subvector extraction

Reviewed By: Peter, efriedma

Differential Revision: https://reviews.llvm.org/D136726

Added: 
    llvm/test/CodeGen/AArch64/aarch64-v1f32-arg.ll

Modified: 
    llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
index 331149bdd05f5..a63e85a2863e5 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -398,10 +398,9 @@ static SDValue getCopyFromPartsVector(SelectionDAG &DAG, const SDLoc &DL,
     if (ValueVT.getSizeInBits() == PartEVT.getSizeInBits())
       return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
 
-    // If the element type of the source/dest vectors are the same, but the
-    // parts vector has more elements than the value vector, then we have a
-    // vector widening case (e.g. <2 x float> -> <4 x float>).  Extract the
-    // elements we want.
+    // If the parts vector has more elements than the value vector, then we
+    // have a vector widening case (e.g. <2 x float> -> <4 x float>).
+    // Extract the elements we want.
     if (PartEVT.getVectorElementCount() != ValueVT.getVectorElementCount()) {
       assert((PartEVT.getVectorElementCount().getKnownMinValue() >
               ValueVT.getVectorElementCount().getKnownMinValue()) &&
@@ -415,6 +414,8 @@ static SDValue getCopyFromPartsVector(SelectionDAG &DAG, const SDLoc &DL,
                         DAG.getVectorIdxConstant(0, DL));
       if (PartEVT == ValueVT)
         return Val;
+      if (PartEVT.isInteger() && ValueVT.isFloatingPoint())
+        return DAG.getNode(ISD::BITCAST, DL, ValueVT, Val);
     }
 
     // Promoted vector extract

diff  --git a/llvm/test/CodeGen/AArch64/aarch64-v1f32-arg.ll b/llvm/test/CodeGen/AArch64/aarch64-v1f32-arg.ll
new file mode 100644
index 0000000000000..1677a7b5d013d
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/aarch64-v1f32-arg.ll
@@ -0,0 +1,11 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=aarch64 | FileCheck %s
+
+define <1 x float> @f(<16 x i64> %0, <1 x float> %1) {
+; CHECK-LABEL: f:
+; CHECK:       // %bb.0: // %BB
+; CHECK-NEXT:    ldr d0, [sp]
+; CHECK-NEXT:    ret
+BB:
+  ret <1 x float> %1
+}