[PATCH] D137363: [RISCV][Codegen] Account for LMUL in Vector Mask instructions

[Michael Maitland via Phabricator via llvm-commits]

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It is likley that subtargets act differently for vector fixed-point arithmetic instructions based on the LMUL. This patch creates seperate SchedRead, SchedWrite, WriteRes, ReadAdvance for each relevant LMUL.

[RISCV][CodeGen] Account for LMUL for Vector Permutation Instructions

It is likley that subtargets act differently for vector fixed-point arithmetic instructions
based on the LMUL. This patch creates seperate SchedRead, SchedWrite, WriteRes, ReadAdvance
for each relevant LMUL.

[RISCV][CodeGen] Account for LMUL for Vector Integer load store instructions

It is likley that subtargets act differently for a vector load store instructions based on the LMUL.
This patch creates seperate SchedRead, SchedWrite, WriteRes, ReadAdvance for each relevant LMUL.

[RISCV][CodeGen] Kill dead pseudo classes and replace with specific LMUL versions

Since changes to account for LMUL in scheduler model existed over patches, we had to keep
both LMUL specific and all LMUL classes around. Now that only the LMUL specific
classes are used, we can remove the old ones.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D137363

Files:
  llvm/lib/Target/RISCV/RISCVInstrInfoV.td
  llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
  llvm/lib/Target/RISCV/RISCVScheduleV.td

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