[PATCH] D130919: [MRI] isConstantPhysReg should also check if the register is clobbered by a RegMask

Thu Nov 3 14:42:45 PDT 2022

Carrot added inline comments.

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Comment at: llvm/test/CodeGen/AMDGPU/GlobalISel/udiv.i64.ll:1
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -global-isel -amdgpu-codegenprepare-disable-idiv-expansion=1 -mtriple=amdgcn-amd-amdpal -denormal-fp-math-f32=preserve-sign -mattr=+mad-mac-f32-insts < %s | FileCheck -check-prefixes=CHECK,GISEL %s
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Carrot wrote:
> foad wrote:
> > I don't understant why these diffs are included in the patch. Can you double check? I don't think your patch affects codegen for any of:
> > ```
> >   LLVM :: CodeGen/AMDGPU/GlobalISel/udiv.i64.ll
> >   LLVM :: CodeGen/AMDGPU/GlobalISel/urem.i64.ll
> >   LLVM :: CodeGen/AMDGPU/sgpr-control-flow.ll
> > ```
> Will investigate it.
They are also caused by the change in MachineCSE. They don't show up in D137222 because there are other changes in MachineCSE::isPRECandidate between the two versions of my two clients. They will disappear after rebaseing.

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D130919/new/

https://reviews.llvm.org/D130919