[PATCH] D137350: [RISCV] Implement assembler support for XVentanaCondOps

[Craig Topper via Phabricator via llvm-commits]

craig.topper added a comment.

In D137350#3906234 <https://reviews.llvm.org/D137350#3906234>, @reames wrote:

> In D137350#3906126 <https://reviews.llvm.org/D137350#3906126>, @craig.topper wrote:
>
>> Do these need their own DecoderNameSpace?
>
> What is a decoder namespace?  Some quick grepping and googling isn't very informative.

If another vendor also uses these opcodes for something else, I think we would need to partition the disassembler tables.

Some existing examples

  RISCVInstrInfoC.td
  330:let DecoderNamespace = "RISCV32Only_",
  364:let DecoderNamespace = "RISCV32Only_",
  409:    DecoderNamespace = "RISCV32Only_", Defs = [X1],
  517:let DecoderNamespace = "RISCV32Only_",
  577:let DecoderNamespace = "RISCV32Only_",

`RISCVDisassembler::getInstruction` checks some subtarget bits to select different tables where there are conflicts.


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