[PATCH] D136858: [AArch64-SVE]: Force generating code compatible to streaming mode for sve-fixed-length tests.

Paul Walker via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Thu Nov 3 13:57:39 PDT 2022


paulwalker-arm added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h:265
+    if(ST->forceStreamingCompatibleSVE())
+      return false;
 
----------------
Matt wrote:
> paulwalker-arm wrote:
> > Matt wrote:
> > > paulwalker-arm wrote:
> > > > Matt wrote:
> > > > > I wonder, would it also make sense to do that for 128-bit vectors (regardless of the streaming mode) as a (temporary?) fix for https://github.com/llvm/llvm-project/issues/56412?
> > > > > @hassnaa-arm, @paulwalker-arm: Thoughts?
> > > > @Matt : That's not a bug we can actually hit though is it? I mean, you have to edit the LLVM code in order to trigger the failure case?
> > > Indeed, I'm asking in the context assuming the modification of `useSVEForFixedLengthVectors`--curious whether a similar fix is applicable, given how similar that modification is to the `forceStreamingCompatibleSVE` special case (that's the only relation to this patch). Chances are it would only be needed for `half`/`fp16`, too.
> > > 
> > I see, then yes.  Doing this will force the intrinsic to be scalarised at the IR level and thus you will not hit the failure case within code generation.  56412 isn't just about 128bit vectors though, because those work today. It's really about restricting smaller than 64bit vectors (e.g. <2 x half>)  when specially targeting SVE128. That said, I'd sooner fix the underlying issue :)
> Makes sense! (Would it be fair to say that the underlying issue is somewhere in SelectionDAG and the interaction of SVE128 and smaller vector?)
Yes.  I'm pretty sure it's a legalisation hang where we keep bouncing between two different legalisation styles.


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