[PATCH] D130897: [schedtool] Add schedtool to generate x86 schedmodel automatically

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added a comment.

@HaohaiWen Something I've noticed is that the autogen AlderlakeP model has a LOT of single match instregex entries (and in fact the regex is written to be a single match) - which are a lot slower to match/compile in llvm-tblgen than instr equivalents - see https://github.com/llvm/llvm-project/issues/35303

I added a dbg dump to InstRegexOp::apply to warn about single intregex matches and many of them are coming from AlderlakeP.

Completely random example (it was just where the I paused the debugger):

  def ADLPWriteResGroup222 : SchedWriteRes<[ADLPPort00_01, ADLPPort00_01_05, ADLPPort00_06, ADLPPort01_05]> {
    let ResourceCycles = [2, 2, 1, 2];
    let Latency = 6;
    let NumMicroOps = 7;
  }
  def : InstRW<[ADLPWriteResGroup222], (instregex "^SHA1MSG2rr$")>;

That could just as well be (instrs SHA1MSG2rr)


Repository:
  rG LLVM Github Monorepo

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https://reviews.llvm.org/D130897