[llvm] 5073ae2 - [AMDGPU] Fix duplicated words in comments

[Jay Foad via llvm-commits]

Author: Jay Foad
Date: 2022-11-03T15:33:30Z
New Revision: 5073ae2a883f2c1dc2d4e81d9f7ed7ffae8d8ba4

URL: https://github.com/llvm/llvm-project/commit/5073ae2a883f2c1dc2d4e81d9f7ed7ffae8d8ba4
DIFF: https://github.com/llvm/llvm-project/commit/5073ae2a883f2c1dc2d4e81d9f7ed7ffae8d8ba4.diff

LOG: [AMDGPU] Fix duplicated words in comments

Added: 
    

Modified: 
    llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
    llvm/lib/Target/AMDGPU/SIISelLowering.cpp
    llvm/lib/Target/AMDGPU/SIInstrInfo.h
    llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
    llvm/lib/Target/AMDGPU/SIOptimizeVGPRLiveRange.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
index dfa3c0af6526..79dc60c93f40 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
@@ -5035,7 +5035,7 @@ bool AMDGPULegalizerInfo::legalizeImageIntrinsic(
   // s16 -> <2 x s16>, and <3 x s16> -> <4 x s16>,
   LLT RoundedTy;
 
-  // S32 vector to to cover all data, plus TFE result element.
+  // S32 vector to cover all data, plus TFE result element.
   LLT TFETy;
 
   // Register type to use for each loaded component. Will be S32 or V2S16.

diff  --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index 24ef9fdb7b8c..eb947a17ef9e 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -10375,7 +10375,7 @@ SDValue SITargetLowering::performFCanonicalizeCombine(
   // If it's free to do so, push canonicalizes further up the source, which may
   // find a canonical source.
   //
-  // TODO: More opcodes. Note this is unsafe for the the _ieee minnum/maxnum for
+  // TODO: More opcodes. Note this is unsafe for the _ieee minnum/maxnum for
   // sNaNs.
   if (SrcOpc == ISD::FMINNUM || SrcOpc == ISD::FMAXNUM) {
     auto *CRHS = dyn_cast<ConstantFPSDNode>(N0.getOperand(1));

diff  --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.h b/llvm/lib/Target/AMDGPU/SIInstrInfo.h
index b80838c393fc..05589010654a 100644
--- a/llvm/lib/Target/AMDGPU/SIInstrInfo.h
+++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.h
@@ -723,7 +723,7 @@ class SIInstrInfo final : public AMDGPUGenInstrInfo {
   }
 
   /// \returns true if this is an s_store_dword* instruction. This is more
-  /// specific than than isSMEM && mayStore.
+  /// specific than isSMEM && mayStore.
   static bool isScalarStore(const MachineInstr &MI) {
     return MI.getDesc().TSFlags & SIInstrFlags::SCALAR_STORE;
   }

diff  --git a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
index f603244086a9..19b74ce319fa 100644
--- a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
+++ b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h
@@ -358,7 +358,7 @@ class SIMachineFunctionInfo final : public AMDGPUMachineFunction {
   // as the input registers.
   Register ScratchRSrcReg = AMDGPU::PRIVATE_RSRC_REG;
 
-  // This is the the unswizzled offset from the current dispatch's scratch wave
+  // This is the unswizzled offset from the current dispatch's scratch wave
   // base to the beginning of the current function's frame.
   Register FrameOffsetReg = AMDGPU::FP_REG;
 
@@ -462,7 +462,7 @@ class SIMachineFunctionInfo final : public AMDGPUMachineFunction {
     // VGPR used for SGPR spills
     Register VGPR;
 
-    // If the VGPR is is used for SGPR spills in a non-entrypoint function, the
+    // If the VGPR is used for SGPR spills in a non-entrypoint function, the
     // stack slot used to save/restore it in the prolog/epilog.
     Optional<int> FI;
 

diff  --git a/llvm/lib/Target/AMDGPU/SIOptimizeVGPRLiveRange.cpp b/llvm/lib/Target/AMDGPU/SIOptimizeVGPRLiveRange.cpp
index 2ae3157bab49..ae2c10116de8 100644
--- a/llvm/lib/Target/AMDGPU/SIOptimizeVGPRLiveRange.cpp
+++ b/llvm/lib/Target/AMDGPU/SIOptimizeVGPRLiveRange.cpp
@@ -36,7 +36,7 @@
 ///  the instructions in bb.then will only overwrite lanes that will never be
 ///  accessed in bb.else.
 ///
-///  This pass aims to to tell register allocator that %a is in-fact dead,
+///  This pass aims to tell register allocator that %a is in-fact dead,
 ///  through inserting a phi-node in bb.flow saying that %a is undef when coming
 ///  from bb.then, and then replace the uses in the bb.else with the result of
 ///  newly inserted phi.