[llvm] 150fc73 - [AggressiveInstCombine] Avoid load merge/widen if stores are present b/w loads
via llvm-commits
llvm-commits at lists.llvm.org
Thu Nov 3 07:32:34 PDT 2022
Author: bipmis
Date: 2022-11-03T14:32:07Z
New Revision: 150fc73ddab65901e2f89c70af436706b859eef8
URL: https://github.com/llvm/llvm-project/commit/150fc73ddab65901e2f89c70af436706b859eef8
DIFF: https://github.com/llvm/llvm-project/commit/150fc73ddab65901e2f89c70af436706b859eef8.diff
LOG: [AggressiveInstCombine] Avoid load merge/widen if stores are present b/w loads
This patch is to address the test cases in which the load has to be inserted at a right point. This happens when there is a store b/w the loads.
This patch reverts the loads merge in all cases when stores are present b/w loads and will eventually be replaced with proper fix and test cases.
Differential Revision: https://reviews.llvm.org/D137333
Added:
Modified:
llvm/lib/Transforms/AggressiveInstCombine/AggressiveInstCombine.cpp
llvm/test/Transforms/AggressiveInstCombine/AArch64/or-load.ll
llvm/test/Transforms/AggressiveInstCombine/X86/or-load.ll
Removed:
################################################################################
diff --git a/llvm/lib/Transforms/AggressiveInstCombine/AggressiveInstCombine.cpp b/llvm/lib/Transforms/AggressiveInstCombine/AggressiveInstCombine.cpp
index 52d0defae63c9..4ce823f526637 100644
--- a/llvm/lib/Transforms/AggressiveInstCombine/AggressiveInstCombine.cpp
+++ b/llvm/lib/Transforms/AggressiveInstCombine/AggressiveInstCombine.cpp
@@ -729,15 +729,15 @@ static bool foldLoadsRecursive(Value *V, LoadOps &LOps, const DataLayout &DL,
if (LoadSize1 < 8 || !isPowerOf2_64(LoadSize1))
return false;
- // Alias Analysis to check for store b/w the loads.
+ // TODO: Alias Analysis to check for stores b/w the loads.
+ // Currently bail out if there are stores b/w the loads.
LoadInst *Start = LI1, *End = LI2;
if (!LI1->comesBefore(LI2))
std::swap(Start, End);
- MemoryLocation Loc = MemoryLocation::get(End);
unsigned NumScanned = 0;
for (Instruction &Inst :
make_range(Start->getIterator(), End->getIterator())) {
- if (Inst.mayWriteToMemory() && isModSet(AA.getModRefInfo(&Inst, Loc)))
+ if (Inst.mayWriteToMemory())
return false;
if (++NumScanned > MaxInstrsToScan)
return false;
diff --git a/llvm/test/Transforms/AggressiveInstCombine/AArch64/or-load.ll b/llvm/test/Transforms/AggressiveInstCombine/AArch64/or-load.ll
index 24febe4ed8fbc..3815d682831d5 100644
--- a/llvm/test/Transforms/AggressiveInstCombine/AArch64/or-load.ll
+++ b/llvm/test/Transforms/AggressiveInstCombine/AArch64/or-load.ll
@@ -142,31 +142,26 @@ define i32 @loadCombine_4consecutive_BE(ptr %p) {
}
define i32 @loadCombine_4consecutive_alias(ptr %p) {
-; LE-LABEL: @loadCombine_4consecutive_alias(
-; LE-NEXT: [[L1:%.*]] = load i32, ptr [[P:%.*]], align 1
-; LE-NEXT: store i8 10, ptr [[P]], align 1
-; LE-NEXT: ret i32 [[L1]]
-;
-; BE-LABEL: @loadCombine_4consecutive_alias(
-; BE-NEXT: [[P1:%.*]] = getelementptr i8, ptr [[P:%.*]], i32 1
-; BE-NEXT: [[P2:%.*]] = getelementptr i8, ptr [[P]], i32 2
-; BE-NEXT: [[P3:%.*]] = getelementptr i8, ptr [[P]], i32 3
-; BE-NEXT: [[L1:%.*]] = load i8, ptr [[P]], align 1
-; BE-NEXT: store i8 10, ptr [[P]], align 1
-; BE-NEXT: [[L2:%.*]] = load i8, ptr [[P1]], align 1
-; BE-NEXT: [[L3:%.*]] = load i8, ptr [[P2]], align 1
-; BE-NEXT: [[L4:%.*]] = load i8, ptr [[P3]], align 1
-; BE-NEXT: [[E1:%.*]] = zext i8 [[L1]] to i32
-; BE-NEXT: [[E2:%.*]] = zext i8 [[L2]] to i32
-; BE-NEXT: [[E3:%.*]] = zext i8 [[L3]] to i32
-; BE-NEXT: [[E4:%.*]] = zext i8 [[L4]] to i32
-; BE-NEXT: [[S2:%.*]] = shl i32 [[E2]], 8
-; BE-NEXT: [[S3:%.*]] = shl i32 [[E3]], 16
-; BE-NEXT: [[S4:%.*]] = shl i32 [[E4]], 24
-; BE-NEXT: [[O1:%.*]] = or i32 [[E1]], [[S2]]
-; BE-NEXT: [[O2:%.*]] = or i32 [[O1]], [[S3]]
-; BE-NEXT: [[O3:%.*]] = or i32 [[O2]], [[S4]]
-; BE-NEXT: ret i32 [[O3]]
+; ALL-LABEL: @loadCombine_4consecutive_alias(
+; ALL-NEXT: [[P1:%.*]] = getelementptr i8, ptr [[P:%.*]], i32 1
+; ALL-NEXT: [[P2:%.*]] = getelementptr i8, ptr [[P]], i32 2
+; ALL-NEXT: [[P3:%.*]] = getelementptr i8, ptr [[P]], i32 3
+; ALL-NEXT: [[L1:%.*]] = load i8, ptr [[P]], align 1
+; ALL-NEXT: store i8 10, ptr [[P]], align 1
+; ALL-NEXT: [[L2:%.*]] = load i8, ptr [[P1]], align 1
+; ALL-NEXT: [[L3:%.*]] = load i8, ptr [[P2]], align 1
+; ALL-NEXT: [[L4:%.*]] = load i8, ptr [[P3]], align 1
+; ALL-NEXT: [[E1:%.*]] = zext i8 [[L1]] to i32
+; ALL-NEXT: [[E2:%.*]] = zext i8 [[L2]] to i32
+; ALL-NEXT: [[E3:%.*]] = zext i8 [[L3]] to i32
+; ALL-NEXT: [[E4:%.*]] = zext i8 [[L4]] to i32
+; ALL-NEXT: [[S2:%.*]] = shl i32 [[E2]], 8
+; ALL-NEXT: [[S3:%.*]] = shl i32 [[E3]], 16
+; ALL-NEXT: [[S4:%.*]] = shl i32 [[E4]], 24
+; ALL-NEXT: [[O1:%.*]] = or i32 [[E1]], [[S2]]
+; ALL-NEXT: [[O2:%.*]] = or i32 [[O1]], [[S3]]
+; ALL-NEXT: [[O3:%.*]] = or i32 [[O2]], [[S4]]
+; ALL-NEXT: ret i32 [[O3]]
;
%p1 = getelementptr i8, ptr %p, i32 1
%p2 = getelementptr i8, ptr %p, i32 2
@@ -193,31 +188,26 @@ define i32 @loadCombine_4consecutive_alias(ptr %p) {
}
define i32 @loadCombine_4consecutive_alias_BE(ptr %p) {
-; LE-LABEL: @loadCombine_4consecutive_alias_BE(
-; LE-NEXT: [[P1:%.*]] = getelementptr i8, ptr [[P:%.*]], i32 1
-; LE-NEXT: [[P2:%.*]] = getelementptr i8, ptr [[P]], i32 2
-; LE-NEXT: [[P3:%.*]] = getelementptr i8, ptr [[P]], i32 3
-; LE-NEXT: [[L1:%.*]] = load i8, ptr [[P]], align 1
-; LE-NEXT: store i8 10, ptr [[P]], align 1
-; LE-NEXT: [[L2:%.*]] = load i8, ptr [[P1]], align 1
-; LE-NEXT: [[L3:%.*]] = load i8, ptr [[P2]], align 1
-; LE-NEXT: [[L4:%.*]] = load i8, ptr [[P3]], align 1
-; LE-NEXT: [[E1:%.*]] = zext i8 [[L1]] to i32
-; LE-NEXT: [[E2:%.*]] = zext i8 [[L2]] to i32
-; LE-NEXT: [[E3:%.*]] = zext i8 [[L3]] to i32
-; LE-NEXT: [[E4:%.*]] = zext i8 [[L4]] to i32
-; LE-NEXT: [[S1:%.*]] = shl i32 [[E1]], 24
-; LE-NEXT: [[S2:%.*]] = shl i32 [[E2]], 16
-; LE-NEXT: [[S3:%.*]] = shl i32 [[E3]], 8
-; LE-NEXT: [[O1:%.*]] = or i32 [[S1]], [[S2]]
-; LE-NEXT: [[O2:%.*]] = or i32 [[O1]], [[S3]]
-; LE-NEXT: [[O3:%.*]] = or i32 [[O2]], [[E4]]
-; LE-NEXT: ret i32 [[O3]]
-;
-; BE-LABEL: @loadCombine_4consecutive_alias_BE(
-; BE-NEXT: [[L1:%.*]] = load i32, ptr [[P:%.*]], align 1
-; BE-NEXT: store i8 10, ptr [[P]], align 1
-; BE-NEXT: ret i32 [[L1]]
+; ALL-LABEL: @loadCombine_4consecutive_alias_BE(
+; ALL-NEXT: [[P1:%.*]] = getelementptr i8, ptr [[P:%.*]], i32 1
+; ALL-NEXT: [[P2:%.*]] = getelementptr i8, ptr [[P]], i32 2
+; ALL-NEXT: [[P3:%.*]] = getelementptr i8, ptr [[P]], i32 3
+; ALL-NEXT: [[L1:%.*]] = load i8, ptr [[P]], align 1
+; ALL-NEXT: store i8 10, ptr [[P]], align 1
+; ALL-NEXT: [[L2:%.*]] = load i8, ptr [[P1]], align 1
+; ALL-NEXT: [[L3:%.*]] = load i8, ptr [[P2]], align 1
+; ALL-NEXT: [[L4:%.*]] = load i8, ptr [[P3]], align 1
+; ALL-NEXT: [[E1:%.*]] = zext i8 [[L1]] to i32
+; ALL-NEXT: [[E2:%.*]] = zext i8 [[L2]] to i32
+; ALL-NEXT: [[E3:%.*]] = zext i8 [[L3]] to i32
+; ALL-NEXT: [[E4:%.*]] = zext i8 [[L4]] to i32
+; ALL-NEXT: [[S1:%.*]] = shl i32 [[E1]], 24
+; ALL-NEXT: [[S2:%.*]] = shl i32 [[E2]], 16
+; ALL-NEXT: [[S3:%.*]] = shl i32 [[E3]], 8
+; ALL-NEXT: [[O1:%.*]] = or i32 [[S1]], [[S2]]
+; ALL-NEXT: [[O2:%.*]] = or i32 [[O1]], [[S3]]
+; ALL-NEXT: [[O3:%.*]] = or i32 [[O2]], [[E4]]
+; ALL-NEXT: ret i32 [[O3]]
;
%p1 = getelementptr i8, ptr %p, i32 1
%p2 = getelementptr i8, ptr %p, i32 2
@@ -1770,32 +1760,26 @@ define i16 @loadCombine_2consecutive_badinsert(ptr %p) {
}
define i32 @loadCombine_4consecutive_badinsert(ptr %p) {
-; LE-LABEL: @loadCombine_4consecutive_badinsert(
-; LE-NEXT: [[P1:%.*]] = getelementptr i8, ptr [[P:%.*]], i32 1
-; LE-NEXT: store i8 0, ptr [[P1]], align 1
-; LE-NEXT: [[L1:%.*]] = load i32, ptr [[P]], align 1
-; LE-NEXT: ret i32 [[L1]]
-;
-; BE-LABEL: @loadCombine_4consecutive_badinsert(
-; BE-NEXT: [[P1:%.*]] = getelementptr i8, ptr [[P:%.*]], i32 1
-; BE-NEXT: [[P2:%.*]] = getelementptr i8, ptr [[P]], i32 2
-; BE-NEXT: [[P3:%.*]] = getelementptr i8, ptr [[P]], i32 3
-; BE-NEXT: [[L2:%.*]] = load i8, ptr [[P1]], align 1
-; BE-NEXT: [[L3:%.*]] = load i8, ptr [[P2]], align 1
-; BE-NEXT: store i8 0, ptr [[P1]], align 1
-; BE-NEXT: [[L4:%.*]] = load i8, ptr [[P3]], align 1
-; BE-NEXT: [[L1:%.*]] = load i8, ptr [[P]], align 1
-; BE-NEXT: [[E1:%.*]] = zext i8 [[L1]] to i32
-; BE-NEXT: [[E2:%.*]] = zext i8 [[L2]] to i32
-; BE-NEXT: [[E3:%.*]] = zext i8 [[L3]] to i32
-; BE-NEXT: [[E4:%.*]] = zext i8 [[L4]] to i32
-; BE-NEXT: [[S2:%.*]] = shl i32 [[E2]], 8
-; BE-NEXT: [[S3:%.*]] = shl i32 [[E3]], 16
-; BE-NEXT: [[S4:%.*]] = shl i32 [[E4]], 24
-; BE-NEXT: [[O1:%.*]] = or i32 [[E1]], [[S2]]
-; BE-NEXT: [[O2:%.*]] = or i32 [[O1]], [[S3]]
-; BE-NEXT: [[O3:%.*]] = or i32 [[O2]], [[S4]]
-; BE-NEXT: ret i32 [[O3]]
+; ALL-LABEL: @loadCombine_4consecutive_badinsert(
+; ALL-NEXT: [[P1:%.*]] = getelementptr i8, ptr [[P:%.*]], i32 1
+; ALL-NEXT: [[P2:%.*]] = getelementptr i8, ptr [[P]], i32 2
+; ALL-NEXT: [[P3:%.*]] = getelementptr i8, ptr [[P]], i32 3
+; ALL-NEXT: [[L2:%.*]] = load i8, ptr [[P1]], align 1
+; ALL-NEXT: [[L3:%.*]] = load i8, ptr [[P2]], align 1
+; ALL-NEXT: store i8 0, ptr [[P1]], align 1
+; ALL-NEXT: [[L4:%.*]] = load i8, ptr [[P3]], align 1
+; ALL-NEXT: [[L1:%.*]] = load i8, ptr [[P]], align 1
+; ALL-NEXT: [[E1:%.*]] = zext i8 [[L1]] to i32
+; ALL-NEXT: [[E2:%.*]] = zext i8 [[L2]] to i32
+; ALL-NEXT: [[E3:%.*]] = zext i8 [[L3]] to i32
+; ALL-NEXT: [[E4:%.*]] = zext i8 [[L4]] to i32
+; ALL-NEXT: [[S2:%.*]] = shl i32 [[E2]], 8
+; ALL-NEXT: [[S3:%.*]] = shl i32 [[E3]], 16
+; ALL-NEXT: [[S4:%.*]] = shl i32 [[E4]], 24
+; ALL-NEXT: [[O1:%.*]] = or i32 [[E1]], [[S2]]
+; ALL-NEXT: [[O2:%.*]] = or i32 [[O1]], [[S3]]
+; ALL-NEXT: [[O3:%.*]] = or i32 [[O2]], [[S4]]
+; ALL-NEXT: ret i32 [[O3]]
;
%p1 = getelementptr i8, ptr %p, i32 1
%p2 = getelementptr i8, ptr %p, i32 2
@@ -1822,32 +1806,26 @@ define i32 @loadCombine_4consecutive_badinsert(ptr %p) {
}
define i32 @loadCombine_4consecutive_badinsert2(ptr %p) {
-; LE-LABEL: @loadCombine_4consecutive_badinsert2(
-; LE-NEXT: [[P3:%.*]] = getelementptr i8, ptr [[P:%.*]], i32 3
-; LE-NEXT: store i8 0, ptr [[P3]], align 1
-; LE-NEXT: [[L1:%.*]] = load i32, ptr [[P]], align 1
-; LE-NEXT: ret i32 [[L1]]
-;
-; BE-LABEL: @loadCombine_4consecutive_badinsert2(
-; BE-NEXT: [[P1:%.*]] = getelementptr i8, ptr [[P:%.*]], i32 1
-; BE-NEXT: [[P2:%.*]] = getelementptr i8, ptr [[P]], i32 2
-; BE-NEXT: [[P3:%.*]] = getelementptr i8, ptr [[P]], i32 3
-; BE-NEXT: [[L2:%.*]] = load i8, ptr [[P1]], align 1
-; BE-NEXT: store i8 0, ptr [[P3]], align 1
-; BE-NEXT: [[L3:%.*]] = load i8, ptr [[P2]], align 1
-; BE-NEXT: [[L4:%.*]] = load i8, ptr [[P3]], align 1
-; BE-NEXT: [[L1:%.*]] = load i8, ptr [[P]], align 1
-; BE-NEXT: [[E1:%.*]] = zext i8 [[L1]] to i32
-; BE-NEXT: [[E2:%.*]] = zext i8 [[L2]] to i32
-; BE-NEXT: [[E3:%.*]] = zext i8 [[L3]] to i32
-; BE-NEXT: [[E4:%.*]] = zext i8 [[L4]] to i32
-; BE-NEXT: [[S2:%.*]] = shl i32 [[E2]], 8
-; BE-NEXT: [[S3:%.*]] = shl i32 [[E3]], 16
-; BE-NEXT: [[S4:%.*]] = shl i32 [[E4]], 24
-; BE-NEXT: [[O1:%.*]] = or i32 [[E1]], [[S2]]
-; BE-NEXT: [[O2:%.*]] = or i32 [[O1]], [[S3]]
-; BE-NEXT: [[O3:%.*]] = or i32 [[O2]], [[S4]]
-; BE-NEXT: ret i32 [[O3]]
+; ALL-LABEL: @loadCombine_4consecutive_badinsert2(
+; ALL-NEXT: [[P1:%.*]] = getelementptr i8, ptr [[P:%.*]], i32 1
+; ALL-NEXT: [[P2:%.*]] = getelementptr i8, ptr [[P]], i32 2
+; ALL-NEXT: [[P3:%.*]] = getelementptr i8, ptr [[P]], i32 3
+; ALL-NEXT: [[L2:%.*]] = load i8, ptr [[P1]], align 1
+; ALL-NEXT: store i8 0, ptr [[P3]], align 1
+; ALL-NEXT: [[L3:%.*]] = load i8, ptr [[P2]], align 1
+; ALL-NEXT: [[L4:%.*]] = load i8, ptr [[P3]], align 1
+; ALL-NEXT: [[L1:%.*]] = load i8, ptr [[P]], align 1
+; ALL-NEXT: [[E1:%.*]] = zext i8 [[L1]] to i32
+; ALL-NEXT: [[E2:%.*]] = zext i8 [[L2]] to i32
+; ALL-NEXT: [[E3:%.*]] = zext i8 [[L3]] to i32
+; ALL-NEXT: [[E4:%.*]] = zext i8 [[L4]] to i32
+; ALL-NEXT: [[S2:%.*]] = shl i32 [[E2]], 8
+; ALL-NEXT: [[S3:%.*]] = shl i32 [[E3]], 16
+; ALL-NEXT: [[S4:%.*]] = shl i32 [[E4]], 24
+; ALL-NEXT: [[O1:%.*]] = or i32 [[E1]], [[S2]]
+; ALL-NEXT: [[O2:%.*]] = or i32 [[O1]], [[S3]]
+; ALL-NEXT: [[O3:%.*]] = or i32 [[O2]], [[S4]]
+; ALL-NEXT: ret i32 [[O3]]
;
%p1 = getelementptr i8, ptr %p, i32 1
%p2 = getelementptr i8, ptr %p, i32 2
diff --git a/llvm/test/Transforms/AggressiveInstCombine/X86/or-load.ll b/llvm/test/Transforms/AggressiveInstCombine/X86/or-load.ll
index 7eb3fc31ba6d6..c8852376d1cac 100644
--- a/llvm/test/Transforms/AggressiveInstCombine/X86/or-load.ll
+++ b/llvm/test/Transforms/AggressiveInstCombine/X86/or-load.ll
@@ -150,31 +150,26 @@ define i32 @loadCombine_4consecutive_BE(ptr %p) {
}
define i32 @loadCombine_4consecutive_alias(ptr %p) {
-; LE-LABEL: @loadCombine_4consecutive_alias(
-; LE-NEXT: [[L1:%.*]] = load i32, ptr [[P:%.*]], align 1
-; LE-NEXT: store i8 10, ptr [[P]], align 1
-; LE-NEXT: ret i32 [[L1]]
-;
-; BE-LABEL: @loadCombine_4consecutive_alias(
-; BE-NEXT: [[P1:%.*]] = getelementptr i8, ptr [[P:%.*]], i32 1
-; BE-NEXT: [[P2:%.*]] = getelementptr i8, ptr [[P]], i32 2
-; BE-NEXT: [[P3:%.*]] = getelementptr i8, ptr [[P]], i32 3
-; BE-NEXT: [[L1:%.*]] = load i8, ptr [[P]], align 1
-; BE-NEXT: store i8 10, ptr [[P]], align 1
-; BE-NEXT: [[L2:%.*]] = load i8, ptr [[P1]], align 1
-; BE-NEXT: [[L3:%.*]] = load i8, ptr [[P2]], align 1
-; BE-NEXT: [[L4:%.*]] = load i8, ptr [[P3]], align 1
-; BE-NEXT: [[E1:%.*]] = zext i8 [[L1]] to i32
-; BE-NEXT: [[E2:%.*]] = zext i8 [[L2]] to i32
-; BE-NEXT: [[E3:%.*]] = zext i8 [[L3]] to i32
-; BE-NEXT: [[E4:%.*]] = zext i8 [[L4]] to i32
-; BE-NEXT: [[S2:%.*]] = shl i32 [[E2]], 8
-; BE-NEXT: [[S3:%.*]] = shl i32 [[E3]], 16
-; BE-NEXT: [[S4:%.*]] = shl i32 [[E4]], 24
-; BE-NEXT: [[O1:%.*]] = or i32 [[E1]], [[S2]]
-; BE-NEXT: [[O2:%.*]] = or i32 [[O1]], [[S3]]
-; BE-NEXT: [[O3:%.*]] = or i32 [[O2]], [[S4]]
-; BE-NEXT: ret i32 [[O3]]
+; ALL-LABEL: @loadCombine_4consecutive_alias(
+; ALL-NEXT: [[P1:%.*]] = getelementptr i8, ptr [[P:%.*]], i32 1
+; ALL-NEXT: [[P2:%.*]] = getelementptr i8, ptr [[P]], i32 2
+; ALL-NEXT: [[P3:%.*]] = getelementptr i8, ptr [[P]], i32 3
+; ALL-NEXT: [[L1:%.*]] = load i8, ptr [[P]], align 1
+; ALL-NEXT: store i8 10, ptr [[P]], align 1
+; ALL-NEXT: [[L2:%.*]] = load i8, ptr [[P1]], align 1
+; ALL-NEXT: [[L3:%.*]] = load i8, ptr [[P2]], align 1
+; ALL-NEXT: [[L4:%.*]] = load i8, ptr [[P3]], align 1
+; ALL-NEXT: [[E1:%.*]] = zext i8 [[L1]] to i32
+; ALL-NEXT: [[E2:%.*]] = zext i8 [[L2]] to i32
+; ALL-NEXT: [[E3:%.*]] = zext i8 [[L3]] to i32
+; ALL-NEXT: [[E4:%.*]] = zext i8 [[L4]] to i32
+; ALL-NEXT: [[S2:%.*]] = shl i32 [[E2]], 8
+; ALL-NEXT: [[S3:%.*]] = shl i32 [[E3]], 16
+; ALL-NEXT: [[S4:%.*]] = shl i32 [[E4]], 24
+; ALL-NEXT: [[O1:%.*]] = or i32 [[E1]], [[S2]]
+; ALL-NEXT: [[O2:%.*]] = or i32 [[O1]], [[S3]]
+; ALL-NEXT: [[O3:%.*]] = or i32 [[O2]], [[S4]]
+; ALL-NEXT: ret i32 [[O3]]
;
%p1 = getelementptr i8, ptr %p, i32 1
%p2 = getelementptr i8, ptr %p, i32 2
@@ -201,31 +196,26 @@ define i32 @loadCombine_4consecutive_alias(ptr %p) {
}
define i32 @loadCombine_4consecutive_alias_BE(ptr %p) {
-; LE-LABEL: @loadCombine_4consecutive_alias_BE(
-; LE-NEXT: [[P1:%.*]] = getelementptr i8, ptr [[P:%.*]], i32 1
-; LE-NEXT: [[P2:%.*]] = getelementptr i8, ptr [[P]], i32 2
-; LE-NEXT: [[P3:%.*]] = getelementptr i8, ptr [[P]], i32 3
-; LE-NEXT: [[L1:%.*]] = load i8, ptr [[P]], align 1
-; LE-NEXT: store i8 10, ptr [[P]], align 1
-; LE-NEXT: [[L2:%.*]] = load i8, ptr [[P1]], align 1
-; LE-NEXT: [[L3:%.*]] = load i8, ptr [[P2]], align 1
-; LE-NEXT: [[L4:%.*]] = load i8, ptr [[P3]], align 1
-; LE-NEXT: [[E1:%.*]] = zext i8 [[L1]] to i32
-; LE-NEXT: [[E2:%.*]] = zext i8 [[L2]] to i32
-; LE-NEXT: [[E3:%.*]] = zext i8 [[L3]] to i32
-; LE-NEXT: [[E4:%.*]] = zext i8 [[L4]] to i32
-; LE-NEXT: [[S1:%.*]] = shl i32 [[E1]], 24
-; LE-NEXT: [[S2:%.*]] = shl i32 [[E2]], 16
-; LE-NEXT: [[S3:%.*]] = shl i32 [[E3]], 8
-; LE-NEXT: [[O1:%.*]] = or i32 [[S1]], [[S2]]
-; LE-NEXT: [[O2:%.*]] = or i32 [[O1]], [[S3]]
-; LE-NEXT: [[O3:%.*]] = or i32 [[O2]], [[E4]]
-; LE-NEXT: ret i32 [[O3]]
-;
-; BE-LABEL: @loadCombine_4consecutive_alias_BE(
-; BE-NEXT: [[L1:%.*]] = load i32, ptr [[P:%.*]], align 1
-; BE-NEXT: store i8 10, ptr [[P]], align 1
-; BE-NEXT: ret i32 [[L1]]
+; ALL-LABEL: @loadCombine_4consecutive_alias_BE(
+; ALL-NEXT: [[P1:%.*]] = getelementptr i8, ptr [[P:%.*]], i32 1
+; ALL-NEXT: [[P2:%.*]] = getelementptr i8, ptr [[P]], i32 2
+; ALL-NEXT: [[P3:%.*]] = getelementptr i8, ptr [[P]], i32 3
+; ALL-NEXT: [[L1:%.*]] = load i8, ptr [[P]], align 1
+; ALL-NEXT: store i8 10, ptr [[P]], align 1
+; ALL-NEXT: [[L2:%.*]] = load i8, ptr [[P1]], align 1
+; ALL-NEXT: [[L3:%.*]] = load i8, ptr [[P2]], align 1
+; ALL-NEXT: [[L4:%.*]] = load i8, ptr [[P3]], align 1
+; ALL-NEXT: [[E1:%.*]] = zext i8 [[L1]] to i32
+; ALL-NEXT: [[E2:%.*]] = zext i8 [[L2]] to i32
+; ALL-NEXT: [[E3:%.*]] = zext i8 [[L3]] to i32
+; ALL-NEXT: [[E4:%.*]] = zext i8 [[L4]] to i32
+; ALL-NEXT: [[S1:%.*]] = shl i32 [[E1]], 24
+; ALL-NEXT: [[S2:%.*]] = shl i32 [[E2]], 16
+; ALL-NEXT: [[S3:%.*]] = shl i32 [[E3]], 8
+; ALL-NEXT: [[O1:%.*]] = or i32 [[S1]], [[S2]]
+; ALL-NEXT: [[O2:%.*]] = or i32 [[O1]], [[S3]]
+; ALL-NEXT: [[O3:%.*]] = or i32 [[O2]], [[E4]]
+; ALL-NEXT: ret i32 [[O3]]
;
%p1 = getelementptr i8, ptr %p, i32 1
%p2 = getelementptr i8, ptr %p, i32 2
@@ -1861,22 +1851,16 @@ define i32 @loadCombine_4consecutive_lower_index_comes_before(ptr %p) {
}
define i16 @loadCombine_2consecutive_badinsert(ptr %p) {
-; LE-LABEL: @loadCombine_2consecutive_badinsert(
-; LE-NEXT: [[P1:%.*]] = getelementptr i8, ptr [[P:%.*]], i32 1
-; LE-NEXT: store i8 0, ptr [[P1]], align 1
-; LE-NEXT: [[L1:%.*]] = load i16, ptr [[P]], align 1
-; LE-NEXT: ret i16 [[L1]]
-;
-; BE-LABEL: @loadCombine_2consecutive_badinsert(
-; BE-NEXT: [[P1:%.*]] = getelementptr i8, ptr [[P:%.*]], i32 1
-; BE-NEXT: [[L2:%.*]] = load i8, ptr [[P1]], align 1
-; BE-NEXT: store i8 0, ptr [[P1]], align 1
-; BE-NEXT: [[L1:%.*]] = load i8, ptr [[P]], align 1
-; BE-NEXT: [[E1:%.*]] = zext i8 [[L1]] to i16
-; BE-NEXT: [[E2:%.*]] = zext i8 [[L2]] to i16
-; BE-NEXT: [[S2:%.*]] = shl i16 [[E2]], 8
-; BE-NEXT: [[O1:%.*]] = or i16 [[E1]], [[S2]]
-; BE-NEXT: ret i16 [[O1]]
+; ALL-LABEL: @loadCombine_2consecutive_badinsert(
+; ALL-NEXT: [[P1:%.*]] = getelementptr i8, ptr [[P:%.*]], i32 1
+; ALL-NEXT: [[L2:%.*]] = load i8, ptr [[P1]], align 1
+; ALL-NEXT: store i8 0, ptr [[P1]], align 1
+; ALL-NEXT: [[L1:%.*]] = load i8, ptr [[P]], align 1
+; ALL-NEXT: [[E1:%.*]] = zext i8 [[L1]] to i16
+; ALL-NEXT: [[E2:%.*]] = zext i8 [[L2]] to i16
+; ALL-NEXT: [[S2:%.*]] = shl i16 [[E2]], 8
+; ALL-NEXT: [[O1:%.*]] = or i16 [[E1]], [[S2]]
+; ALL-NEXT: ret i16 [[O1]]
;
%p1 = getelementptr i8, ptr %p, i32 1
%l2 = load i8, ptr %p1
@@ -1890,32 +1874,26 @@ define i16 @loadCombine_2consecutive_badinsert(ptr %p) {
}
define i32 @loadCombine_4consecutive_badinsert(ptr %p) {
-; LE-LABEL: @loadCombine_4consecutive_badinsert(
-; LE-NEXT: [[P1:%.*]] = getelementptr i8, ptr [[P:%.*]], i32 1
-; LE-NEXT: store i8 0, ptr [[P1]], align 1
-; LE-NEXT: [[L1:%.*]] = load i32, ptr [[P]], align 1
-; LE-NEXT: ret i32 [[L1]]
-;
-; BE-LABEL: @loadCombine_4consecutive_badinsert(
-; BE-NEXT: [[P1:%.*]] = getelementptr i8, ptr [[P:%.*]], i32 1
-; BE-NEXT: [[P2:%.*]] = getelementptr i8, ptr [[P]], i32 2
-; BE-NEXT: [[P3:%.*]] = getelementptr i8, ptr [[P]], i32 3
-; BE-NEXT: [[L2:%.*]] = load i8, ptr [[P1]], align 1
-; BE-NEXT: [[L3:%.*]] = load i8, ptr [[P2]], align 1
-; BE-NEXT: store i8 0, ptr [[P1]], align 1
-; BE-NEXT: [[L4:%.*]] = load i8, ptr [[P3]], align 1
-; BE-NEXT: [[L1:%.*]] = load i8, ptr [[P]], align 1
-; BE-NEXT: [[E1:%.*]] = zext i8 [[L1]] to i32
-; BE-NEXT: [[E2:%.*]] = zext i8 [[L2]] to i32
-; BE-NEXT: [[E3:%.*]] = zext i8 [[L3]] to i32
-; BE-NEXT: [[E4:%.*]] = zext i8 [[L4]] to i32
-; BE-NEXT: [[S2:%.*]] = shl i32 [[E2]], 8
-; BE-NEXT: [[S3:%.*]] = shl i32 [[E3]], 16
-; BE-NEXT: [[S4:%.*]] = shl i32 [[E4]], 24
-; BE-NEXT: [[O1:%.*]] = or i32 [[E1]], [[S2]]
-; BE-NEXT: [[O2:%.*]] = or i32 [[O1]], [[S3]]
-; BE-NEXT: [[O3:%.*]] = or i32 [[O2]], [[S4]]
-; BE-NEXT: ret i32 [[O3]]
+; ALL-LABEL: @loadCombine_4consecutive_badinsert(
+; ALL-NEXT: [[P1:%.*]] = getelementptr i8, ptr [[P:%.*]], i32 1
+; ALL-NEXT: [[P2:%.*]] = getelementptr i8, ptr [[P]], i32 2
+; ALL-NEXT: [[P3:%.*]] = getelementptr i8, ptr [[P]], i32 3
+; ALL-NEXT: [[L2:%.*]] = load i8, ptr [[P1]], align 1
+; ALL-NEXT: [[L3:%.*]] = load i8, ptr [[P2]], align 1
+; ALL-NEXT: store i8 0, ptr [[P1]], align 1
+; ALL-NEXT: [[L4:%.*]] = load i8, ptr [[P3]], align 1
+; ALL-NEXT: [[L1:%.*]] = load i8, ptr [[P]], align 1
+; ALL-NEXT: [[E1:%.*]] = zext i8 [[L1]] to i32
+; ALL-NEXT: [[E2:%.*]] = zext i8 [[L2]] to i32
+; ALL-NEXT: [[E3:%.*]] = zext i8 [[L3]] to i32
+; ALL-NEXT: [[E4:%.*]] = zext i8 [[L4]] to i32
+; ALL-NEXT: [[S2:%.*]] = shl i32 [[E2]], 8
+; ALL-NEXT: [[S3:%.*]] = shl i32 [[E3]], 16
+; ALL-NEXT: [[S4:%.*]] = shl i32 [[E4]], 24
+; ALL-NEXT: [[O1:%.*]] = or i32 [[E1]], [[S2]]
+; ALL-NEXT: [[O2:%.*]] = or i32 [[O1]], [[S3]]
+; ALL-NEXT: [[O3:%.*]] = or i32 [[O2]], [[S4]]
+; ALL-NEXT: ret i32 [[O3]]
;
%p1 = getelementptr i8, ptr %p, i32 1
%p2 = getelementptr i8, ptr %p, i32 2
@@ -1942,32 +1920,26 @@ define i32 @loadCombine_4consecutive_badinsert(ptr %p) {
}
define i32 @loadCombine_4consecutive_badinsert2(ptr %p) {
-; LE-LABEL: @loadCombine_4consecutive_badinsert2(
-; LE-NEXT: [[P3:%.*]] = getelementptr i8, ptr [[P:%.*]], i32 3
-; LE-NEXT: store i8 0, ptr [[P3]], align 1
-; LE-NEXT: [[L1:%.*]] = load i32, ptr [[P]], align 1
-; LE-NEXT: ret i32 [[L1]]
-;
-; BE-LABEL: @loadCombine_4consecutive_badinsert2(
-; BE-NEXT: [[P1:%.*]] = getelementptr i8, ptr [[P:%.*]], i32 1
-; BE-NEXT: [[P2:%.*]] = getelementptr i8, ptr [[P]], i32 2
-; BE-NEXT: [[P3:%.*]] = getelementptr i8, ptr [[P]], i32 3
-; BE-NEXT: [[L2:%.*]] = load i8, ptr [[P1]], align 1
-; BE-NEXT: store i8 0, ptr [[P3]], align 1
-; BE-NEXT: [[L3:%.*]] = load i8, ptr [[P2]], align 1
-; BE-NEXT: [[L4:%.*]] = load i8, ptr [[P3]], align 1
-; BE-NEXT: [[L1:%.*]] = load i8, ptr [[P]], align 1
-; BE-NEXT: [[E1:%.*]] = zext i8 [[L1]] to i32
-; BE-NEXT: [[E2:%.*]] = zext i8 [[L2]] to i32
-; BE-NEXT: [[E3:%.*]] = zext i8 [[L3]] to i32
-; BE-NEXT: [[E4:%.*]] = zext i8 [[L4]] to i32
-; BE-NEXT: [[S2:%.*]] = shl i32 [[E2]], 8
-; BE-NEXT: [[S3:%.*]] = shl i32 [[E3]], 16
-; BE-NEXT: [[S4:%.*]] = shl i32 [[E4]], 24
-; BE-NEXT: [[O1:%.*]] = or i32 [[E1]], [[S2]]
-; BE-NEXT: [[O2:%.*]] = or i32 [[O1]], [[S3]]
-; BE-NEXT: [[O3:%.*]] = or i32 [[O2]], [[S4]]
-; BE-NEXT: ret i32 [[O3]]
+; ALL-LABEL: @loadCombine_4consecutive_badinsert2(
+; ALL-NEXT: [[P1:%.*]] = getelementptr i8, ptr [[P:%.*]], i32 1
+; ALL-NEXT: [[P2:%.*]] = getelementptr i8, ptr [[P]], i32 2
+; ALL-NEXT: [[P3:%.*]] = getelementptr i8, ptr [[P]], i32 3
+; ALL-NEXT: [[L2:%.*]] = load i8, ptr [[P1]], align 1
+; ALL-NEXT: store i8 0, ptr [[P3]], align 1
+; ALL-NEXT: [[L3:%.*]] = load i8, ptr [[P2]], align 1
+; ALL-NEXT: [[L4:%.*]] = load i8, ptr [[P3]], align 1
+; ALL-NEXT: [[L1:%.*]] = load i8, ptr [[P]], align 1
+; ALL-NEXT: [[E1:%.*]] = zext i8 [[L1]] to i32
+; ALL-NEXT: [[E2:%.*]] = zext i8 [[L2]] to i32
+; ALL-NEXT: [[E3:%.*]] = zext i8 [[L3]] to i32
+; ALL-NEXT: [[E4:%.*]] = zext i8 [[L4]] to i32
+; ALL-NEXT: [[S2:%.*]] = shl i32 [[E2]], 8
+; ALL-NEXT: [[S3:%.*]] = shl i32 [[E3]], 16
+; ALL-NEXT: [[S4:%.*]] = shl i32 [[E4]], 24
+; ALL-NEXT: [[O1:%.*]] = or i32 [[E1]], [[S2]]
+; ALL-NEXT: [[O2:%.*]] = or i32 [[O1]], [[S3]]
+; ALL-NEXT: [[O3:%.*]] = or i32 [[O2]], [[S4]]
+; ALL-NEXT: ret i32 [[O3]]
;
%p1 = getelementptr i8, ptr %p, i32 1
%p2 = getelementptr i8, ptr %p, i32 2
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