[llvm] 9df924a - [PowerPC] Add new DMR register classes to Future CPU.
Stefan Pintilie via llvm-commits
llvm-commits at lists.llvm.org
Thu Nov 3 06:30:01 PDT 2022
Author: Stefan Pintilie
Date: 2022-11-03T08:29:55-05:00
New Revision: 9df924a634ac5ea702b0d8d0d8b737c819a98095
URL: https://github.com/llvm/llvm-project/commit/9df924a634ac5ea702b0d8d0d8b737c819a98095
DIFF: https://github.com/llvm/llvm-project/commit/9df924a634ac5ea702b0d8d0d8b737c819a98095.diff
LOG: [PowerPC] Add new DMR register classes to Future CPU.
A new register class as well as a number of related subregisters are being added
to Future CPU. These registers are Dense Math Registers (DMR) and are 1024 bits
long. These regsiters can also be used in consecutive pairs which leads to a
register that is 2048 bits.
This patch also adds 7 new instructions that use these registers. More
instructions will be added in future patches.
Reviewed By: amyk, saghir
Differential Revision: https://reviews.llvm.org/D136366
Added:
llvm/lib/Target/PowerPC/PPCInstrFuture.td
llvm/lib/Target/PowerPC/PPCInstrFutureMMA.td
llvm/lib/Target/PowerPC/PPCRegisterInfoDMR.td
llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt
llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt
llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s
Modified:
llvm/include/llvm/CodeGen/ValueTypes.td
llvm/include/llvm/IR/Intrinsics.td
llvm/include/llvm/Support/MachineValueType.h
llvm/lib/CodeGen/ValueTypes.cpp
llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp
llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h
llvm/lib/Target/PowerPC/PPCInstrInfo.td
llvm/lib/Target/PowerPC/PPCRegisterInfo.h
llvm/lib/Target/PowerPC/PPCRegisterInfo.td
llvm/lib/Target/PowerPC/PPCScheduleP9.td
llvm/test/CodeGen/PowerPC/future-check-features.ll
llvm/utils/TableGen/CodeGenTarget.cpp
Removed:
################################################################################
diff --git a/llvm/include/llvm/CodeGen/ValueTypes.td b/llvm/include/llvm/CodeGen/ValueTypes.td
index 8ed27f1a0c568..9fc145551880f 100644
--- a/llvm/include/llvm/CodeGen/ValueTypes.td
+++ b/llvm/include/llvm/CodeGen/ValueTypes.td
@@ -47,186 +47,187 @@ def v128i1 : ValueType<128, 24>; // 128 x i1 vector value
def v256i1 : ValueType<256, 25>; // 256 x i1 vector value
def v512i1 : ValueType<512, 26>; // 512 x i1 vector value
def v1024i1 : ValueType<1024, 27>; // 1024 x i1 vector value
-
-def v128i2 : ValueType<256, 28>; // 128 x i2 vector value
-def v256i2 : ValueType<512, 29>; // 256 x i2 vector value
-
-def v64i4 : ValueType<256, 30>; // 64 x i4 vector value
-def v128i4 : ValueType<512, 31>; // 128 x i4 vector value
-
-def v1i8 : ValueType<8, 32>; // 1 x i8 vector value
-def v2i8 : ValueType<16, 33>; // 2 x i8 vector value
-def v4i8 : ValueType<32, 34>; // 4 x i8 vector value
-def v8i8 : ValueType<64, 35>; // 8 x i8 vector value
-def v16i8 : ValueType<128, 36>; // 16 x i8 vector value
-def v32i8 : ValueType<256, 37>; // 32 x i8 vector value
-def v64i8 : ValueType<512, 38>; // 64 x i8 vector value
-def v128i8 : ValueType<1024, 39>; // 128 x i8 vector value
-def v256i8 : ValueType<2048, 40>; // 256 x i8 vector value
-def v512i8 : ValueType<4096, 41>; // 512 x i8 vector value
-def v1024i8 : ValueType<8192, 42>; // 1024 x i8 vector value
-
-def v1i16 : ValueType<16, 43>; // 1 x i16 vector value
-def v2i16 : ValueType<32, 44>; // 2 x i16 vector value
-def v3i16 : ValueType<48, 45>; // 3 x i16 vector value
-def v4i16 : ValueType<64, 46>; // 4 x i16 vector value
-def v8i16 : ValueType<128, 47>; // 8 x i16 vector value
-def v16i16 : ValueType<256, 48>; // 16 x i16 vector value
-def v32i16 : ValueType<512, 49>; // 32 x i16 vector value
-def v64i16 : ValueType<1024, 50>; // 64 x i16 vector value
-def v128i16 : ValueType<2048, 51>; // 128 x i16 vector value
-def v256i16 : ValueType<4096, 52>; // 256 x i16 vector value
-def v512i16 : ValueType<8192, 53>; // 512 x i16 vector value
-
-def v1i32 : ValueType<32, 54>; // 1 x i32 vector value
-def v2i32 : ValueType<64, 55>; // 2 x i32 vector value
-def v3i32 : ValueType<96, 56>; // 3 x i32 vector value
-def v4i32 : ValueType<128, 57>; // 4 x i32 vector value
-def v5i32 : ValueType<160, 58>; // 5 x i32 vector value
-def v6i32 : ValueType<192, 59>; // 6 x f32 vector value
-def v7i32 : ValueType<224, 60>; // 7 x f32 vector value
-def v8i32 : ValueType<256, 61>; // 8 x i32 vector value
-def v16i32 : ValueType<512, 62>; // 16 x i32 vector value
-def v32i32 : ValueType<1024, 63>; // 32 x i32 vector value
-def v64i32 : ValueType<2048, 64>; // 64 x i32 vector value
-def v128i32 : ValueType<4096, 65>; // 128 x i32 vector value
-def v256i32 : ValueType<8192, 66>; // 256 x i32 vector value
-def v512i32 : ValueType<16384, 67>; // 512 x i32 vector value
-def v1024i32 : ValueType<32768, 68>; // 1024 x i32 vector value
-def v2048i32 : ValueType<65536, 69>; // 2048 x i32 vector value
-
-def v1i64 : ValueType<64, 70>; // 1 x i64 vector value
-def v2i64 : ValueType<128, 71>; // 2 x i64 vector value
-def v3i64 : ValueType<192, 72>; // 3 x i64 vector value
-def v4i64 : ValueType<256, 73>; // 4 x i64 vector value
-def v8i64 : ValueType<512, 74>; // 8 x i64 vector value
-def v16i64 : ValueType<1024, 75>; // 16 x i64 vector value
-def v32i64 : ValueType<2048, 76>; // 32 x i64 vector value
-def v64i64 : ValueType<4096, 77>; // 64 x i64 vector value
-def v128i64 : ValueType<8192, 78>; // 128 x i64 vector value
-def v256i64 : ValueType<16384, 79>; // 256 x i64 vector value
-
-def v1i128 : ValueType<128, 80>; // 1 x i128 vector value
-
-def v1f16 : ValueType<16, 81>; // 1 x f16 vector value
-def v2f16 : ValueType<32, 82>; // 2 x f16 vector value
-def v3f16 : ValueType<48, 83>; // 3 x f16 vector value
-def v4f16 : ValueType<64, 84>; // 4 x f16 vector value
-def v8f16 : ValueType<128, 85>; // 8 x f16 vector value
-def v16f16 : ValueType<256, 86>; // 16 x f16 vector value
-def v32f16 : ValueType<512, 87>; // 32 x f16 vector value
-def v64f16 : ValueType<1024, 88>; // 64 x f16 vector value
-def v128f16 : ValueType<2048, 89>; // 128 x f16 vector value
-def v256f16 : ValueType<4096, 90>; // 256 x f16 vector value
-def v512f16 : ValueType<8192, 91>; // 512 x f16 vector value
-
-def v2bf16 : ValueType<32, 92>; // 2 x bf16 vector value
-def v3bf16 : ValueType<48, 93>; // 3 x bf16 vector value
-def v4bf16 : ValueType<64, 94>; // 4 x bf16 vector value
-def v8bf16 : ValueType<128, 95>; // 8 x bf16 vector value
-def v16bf16 : ValueType<256, 96>; // 16 x bf16 vector value
-def v32bf16 : ValueType<512, 97>; // 32 x bf16 vector value
-def v64bf16 : ValueType<1024, 98>; // 64 x bf16 vector value
-def v128bf16 : ValueType<2048, 99>; // 128 x bf16 vector value
-
-def v1f32 : ValueType<32, 100>; // 1 x f32 vector value
-def v2f32 : ValueType<64, 101>; // 2 x f32 vector value
-def v3f32 : ValueType<96, 102>; // 3 x f32 vector value
-def v4f32 : ValueType<128, 103>; // 4 x f32 vector value
-def v5f32 : ValueType<160, 104>; // 5 x f32 vector value
-def v6f32 : ValueType<192, 105>; // 6 x f32 vector value
-def v7f32 : ValueType<224, 106>; // 7 x f32 vector value
-def v8f32 : ValueType<256, 107>; // 8 x f32 vector value
-def v16f32 : ValueType<512, 108>; // 16 x f32 vector value
-def v32f32 : ValueType<1024, 109>; // 32 x f32 vector value
-def v64f32 : ValueType<2048, 110>; // 64 x f32 vector value
-def v128f32 : ValueType<4096, 111>; // 128 x f32 vector value
-def v256f32 : ValueType<8192, 112>; // 256 x f32 vector value
-def v512f32 : ValueType<16384, 113>; // 512 x f32 vector value
-def v1024f32 : ValueType<32768, 114>; // 1024 x f32 vector value
-def v2048f32 : ValueType<65536, 115>; // 2048 x f32 vector value
-
-def v1f64 : ValueType<64, 116>; // 1 x f64 vector value
-def v2f64 : ValueType<128, 117>; // 2 x f64 vector value
-def v3f64 : ValueType<192, 118>; // 3 x f64 vector value
-def v4f64 : ValueType<256, 119>; // 4 x f64 vector value
-def v8f64 : ValueType<512, 120>; // 8 x f64 vector value
-def v16f64 : ValueType<1024, 121>; // 16 x f64 vector value
-def v32f64 : ValueType<2048, 122>; // 32 x f64 vector value
-def v64f64 : ValueType<4096, 123>; // 64 x f64 vector value
-def v128f64 : ValueType<8192, 124>; // 128 x f64 vector value
-def v256f64 : ValueType<16384, 125>; // 256 x f64 vector value
-
-def nxv1i1 : ValueType<1, 126>; // n x 1 x i1 vector value
-def nxv2i1 : ValueType<2, 127>; // n x 2 x i1 vector value
-def nxv4i1 : ValueType<4, 128>; // n x 4 x i1 vector value
-def nxv8i1 : ValueType<8, 129>; // n x 8 x i1 vector value
-def nxv16i1 : ValueType<16, 130>; // n x 16 x i1 vector value
-def nxv32i1 : ValueType<32, 131>; // n x 32 x i1 vector value
-def nxv64i1 : ValueType<64, 132>; // n x 64 x i1 vector value
-
-def nxv1i8 : ValueType<8, 133>; // n x 1 x i8 vector value
-def nxv2i8 : ValueType<16, 134>; // n x 2 x i8 vector value
-def nxv4i8 : ValueType<32, 135>; // n x 4 x i8 vector value
-def nxv8i8 : ValueType<64, 136>; // n x 8 x i8 vector value
-def nxv16i8 : ValueType<128, 137>; // n x 16 x i8 vector value
-def nxv32i8 : ValueType<256, 138>; // n x 32 x i8 vector value
-def nxv64i8 : ValueType<512, 139>; // n x 64 x i8 vector value
-
-def nxv1i16 : ValueType<16, 140>; // n x 1 x i16 vector value
-def nxv2i16 : ValueType<32, 141>; // n x 2 x i16 vector value
-def nxv4i16 : ValueType<64, 142>; // n x 4 x i16 vector value
-def nxv8i16 : ValueType<128, 143>; // n x 8 x i16 vector value
-def nxv16i16 : ValueType<256, 144>; // n x 16 x i16 vector value
-def nxv32i16 : ValueType<512, 145>; // n x 32 x i16 vector value
-
-def nxv1i32 : ValueType<32, 146>; // n x 1 x i32 vector value
-def nxv2i32 : ValueType<64, 147>; // n x 2 x i32 vector value
-def nxv4i32 : ValueType<128, 148>; // n x 4 x i32 vector value
-def nxv8i32 : ValueType<256, 149>; // n x 8 x i32 vector value
-def nxv16i32 : ValueType<512, 150>; // n x 16 x i32 vector value
-def nxv32i32 : ValueType<1024, 151>; // n x 32 x i32 vector value
-
-def nxv1i64 : ValueType<64, 152>; // n x 1 x i64 vector value
-def nxv2i64 : ValueType<128, 153>; // n x 2 x i64 vector value
-def nxv4i64 : ValueType<256, 154>; // n x 4 x i64 vector value
-def nxv8i64 : ValueType<512, 155>; // n x 8 x i64 vector value
-def nxv16i64 : ValueType<1024, 156>; // n x 16 x i64 vector value
-def nxv32i64 : ValueType<2048, 157>; // n x 32 x i64 vector value
-
-def nxv1f16 : ValueType<16, 158>; // n x 1 x f16 vector value
-def nxv2f16 : ValueType<32, 159>; // n x 2 x f16 vector value
-def nxv4f16 : ValueType<64, 160>; // n x 4 x f16 vector value
-def nxv8f16 : ValueType<128, 161>; // n x 8 x f16 vector value
-def nxv16f16 : ValueType<256, 162>; // n x 16 x f16 vector value
-def nxv32f16 : ValueType<512, 163>; // n x 32 x f16 vector value
-
-def nxv1bf16 : ValueType<16, 164>; // n x 1 x bf16 vector value
-def nxv2bf16 : ValueType<32, 165>; // n x 2 x bf16 vector value
-def nxv4bf16 : ValueType<64, 166>; // n x 4 x bf16 vector value
-def nxv8bf16 : ValueType<128, 167>; // n x 8 x bf16 vector value
-def nxv16bf16 : ValueType<256, 168>; // n x 16 x bf16 vector value
-def nxv32bf16 : ValueType<512, 169>; // n x 32 x bf16 vector value
-
-def nxv1f32 : ValueType<32, 170>; // n x 1 x f32 vector value
-def nxv2f32 : ValueType<64, 171>; // n x 2 x f32 vector value
-def nxv4f32 : ValueType<128, 172>; // n x 4 x f32 vector value
-def nxv8f32 : ValueType<256, 173>; // n x 8 x f32 vector value
-def nxv16f32 : ValueType<512, 174>; // n x 16 x f32 vector value
-
-def nxv1f64 : ValueType<64, 175>; // n x 1 x f64 vector value
-def nxv2f64 : ValueType<128, 176>; // n x 2 x f64 vector value
-def nxv4f64 : ValueType<256, 177>; // n x 4 x f64 vector value
-def nxv8f64 : ValueType<512, 178>; // n x 8 x f64 vector value
-
-def x86mmx : ValueType<64, 179>; // X86 MMX value
-def FlagVT : ValueType<0, 180>; // Pre-RA sched glue
-def isVoid : ValueType<0, 181>; // Produces no value
-def untyped : ValueType<8, 182>; // Produces an untyped value
-def funcref : ValueType<0, 183>; // WebAssembly's funcref type
-def externref : ValueType<0, 184>; // WebAssembly's externref type
-def x86amx : ValueType<8192, 185>; // X86 AMX value
-def i64x8 : ValueType<512, 186>; // 8 Consecutive GPRs (AArch64)
+def v2048i1 : ValueType<2048, 28>; // 2048 x i1 vector value
+
+def v128i2 : ValueType<256, 29>; // 128 x i2 vector value
+def v256i2 : ValueType<512, 30>; // 256 x i2 vector value
+
+def v64i4 : ValueType<256, 31>; // 64 x i4 vector value
+def v128i4 : ValueType<512, 32>; // 128 x i4 vector value
+
+def v1i8 : ValueType<8, 33>; // 1 x i8 vector value
+def v2i8 : ValueType<16, 34>; // 2 x i8 vector value
+def v4i8 : ValueType<32, 35>; // 4 x i8 vector value
+def v8i8 : ValueType<64, 36>; // 8 x i8 vector value
+def v16i8 : ValueType<128, 37>; // 16 x i8 vector value
+def v32i8 : ValueType<256, 38>; // 32 x i8 vector value
+def v64i8 : ValueType<512, 39>; // 64 x i8 vector value
+def v128i8 : ValueType<1024, 40>; // 128 x i8 vector value
+def v256i8 : ValueType<2048, 41>; // 256 x i8 vector value
+def v512i8 : ValueType<4096, 42>; // 512 x i8 vector value
+def v1024i8 : ValueType<8192, 43>; // 1024 x i8 vector value
+
+def v1i16 : ValueType<16, 44>; // 1 x i16 vector value
+def v2i16 : ValueType<32, 45>; // 2 x i16 vector value
+def v3i16 : ValueType<48, 46>; // 3 x i16 vector value
+def v4i16 : ValueType<64, 47>; // 4 x i16 vector value
+def v8i16 : ValueType<128, 48>; // 8 x i16 vector value
+def v16i16 : ValueType<256, 49>; // 16 x i16 vector value
+def v32i16 : ValueType<512, 50>; // 32 x i16 vector value
+def v64i16 : ValueType<1024, 51>; // 64 x i16 vector value
+def v128i16 : ValueType<2048, 52>; // 128 x i16 vector value
+def v256i16 : ValueType<4096, 53>; // 256 x i16 vector value
+def v512i16 : ValueType<8192, 54>; // 512 x i16 vector value
+
+def v1i32 : ValueType<32, 55>; // 1 x i32 vector value
+def v2i32 : ValueType<64, 56>; // 2 x i32 vector value
+def v3i32 : ValueType<96, 57>; // 3 x i32 vector value
+def v4i32 : ValueType<128, 58>; // 4 x i32 vector value
+def v5i32 : ValueType<160, 59>; // 5 x i32 vector value
+def v6i32 : ValueType<192, 60>; // 6 x f32 vector value
+def v7i32 : ValueType<224, 61>; // 7 x f32 vector value
+def v8i32 : ValueType<256, 62>; // 8 x i32 vector value
+def v16i32 : ValueType<512, 63>; // 16 x i32 vector value
+def v32i32 : ValueType<1024, 64>; // 32 x i32 vector value
+def v64i32 : ValueType<2048, 65>; // 64 x i32 vector value
+def v128i32 : ValueType<4096, 66>; // 128 x i32 vector value
+def v256i32 : ValueType<8192, 67>; // 256 x i32 vector value
+def v512i32 : ValueType<16384, 68>; // 512 x i32 vector value
+def v1024i32 : ValueType<32768, 69>; // 1024 x i32 vector value
+def v2048i32 : ValueType<65536, 70>; // 2048 x i32 vector value
+
+def v1i64 : ValueType<64, 71>; // 1 x i64 vector value
+def v2i64 : ValueType<128, 72>; // 2 x i64 vector value
+def v3i64 : ValueType<192, 73>; // 3 x i64 vector value
+def v4i64 : ValueType<256, 74>; // 4 x i64 vector value
+def v8i64 : ValueType<512, 75>; // 8 x i64 vector value
+def v16i64 : ValueType<1024, 76>; // 16 x i64 vector value
+def v32i64 : ValueType<2048, 77>; // 32 x i64 vector value
+def v64i64 : ValueType<4096, 78>; // 64 x i64 vector value
+def v128i64 : ValueType<8192, 79>; // 128 x i64 vector value
+def v256i64 : ValueType<16384, 80>; // 256 x i64 vector value
+
+def v1i128 : ValueType<128, 81>; // 1 x i128 vector value
+
+def v1f16 : ValueType<16, 82>; // 1 x f16 vector value
+def v2f16 : ValueType<32, 83>; // 2 x f16 vector value
+def v3f16 : ValueType<48, 84>; // 3 x f16 vector value
+def v4f16 : ValueType<64, 85>; // 4 x f16 vector value
+def v8f16 : ValueType<128, 86>; // 8 x f16 vector value
+def v16f16 : ValueType<256, 87>; // 16 x f16 vector value
+def v32f16 : ValueType<512, 88>; // 32 x f16 vector value
+def v64f16 : ValueType<1024, 89>; // 64 x f16 vector value
+def v128f16 : ValueType<2048, 90>; // 128 x f16 vector value
+def v256f16 : ValueType<4096, 91>; // 256 x f16 vector value
+def v512f16 : ValueType<8192, 92>; // 512 x f16 vector value
+
+def v2bf16 : ValueType<32, 93>; // 2 x bf16 vector value
+def v3bf16 : ValueType<48, 94>; // 3 x bf16 vector value
+def v4bf16 : ValueType<64, 95>; // 4 x bf16 vector value
+def v8bf16 : ValueType<128, 96>; // 8 x bf16 vector value
+def v16bf16 : ValueType<256, 97>; // 16 x bf16 vector value
+def v32bf16 : ValueType<512, 98>; // 32 x bf16 vector value
+def v64bf16 : ValueType<1024, 99>; // 64 x bf16 vector value
+def v128bf16 : ValueType<2048, 100>; // 128 x bf16 vector value
+
+def v1f32 : ValueType<32, 101>; // 1 x f32 vector value
+def v2f32 : ValueType<64, 102>; // 2 x f32 vector value
+def v3f32 : ValueType<96, 103>; // 3 x f32 vector value
+def v4f32 : ValueType<128, 104>; // 4 x f32 vector value
+def v5f32 : ValueType<160, 105>; // 5 x f32 vector value
+def v6f32 : ValueType<192, 106>; // 6 x f32 vector value
+def v7f32 : ValueType<224, 107>; // 7 x f32 vector value
+def v8f32 : ValueType<256, 108>; // 8 x f32 vector value
+def v16f32 : ValueType<512, 109>; // 16 x f32 vector value
+def v32f32 : ValueType<1024, 110>; // 32 x f32 vector value
+def v64f32 : ValueType<2048, 111>; // 64 x f32 vector value
+def v128f32 : ValueType<4096, 112>; // 128 x f32 vector value
+def v256f32 : ValueType<8192, 113>; // 256 x f32 vector value
+def v512f32 : ValueType<16384, 114>; // 512 x f32 vector value
+def v1024f32 : ValueType<32768, 115>; // 1024 x f32 vector value
+def v2048f32 : ValueType<65536, 116>; // 2048 x f32 vector value
+
+def v1f64 : ValueType<64, 117>; // 1 x f64 vector value
+def v2f64 : ValueType<128, 118>; // 2 x f64 vector value
+def v3f64 : ValueType<192, 119>; // 3 x f64 vector value
+def v4f64 : ValueType<256, 120>; // 4 x f64 vector value
+def v8f64 : ValueType<512, 121>; // 8 x f64 vector value
+def v16f64 : ValueType<1024, 122>; // 16 x f64 vector value
+def v32f64 : ValueType<2048, 123>; // 32 x f64 vector value
+def v64f64 : ValueType<4096, 124>; // 64 x f64 vector value
+def v128f64 : ValueType<8192, 125>; // 128 x f64 vector value
+def v256f64 : ValueType<16384, 126>; // 256 x f64 vector value
+
+def nxv1i1 : ValueType<1, 127>; // n x 1 x i1 vector value
+def nxv2i1 : ValueType<2, 128>; // n x 2 x i1 vector value
+def nxv4i1 : ValueType<4, 129>; // n x 4 x i1 vector value
+def nxv8i1 : ValueType<8, 130>; // n x 8 x i1 vector value
+def nxv16i1 : ValueType<16, 131>; // n x 16 x i1 vector value
+def nxv32i1 : ValueType<32, 132>; // n x 32 x i1 vector value
+def nxv64i1 : ValueType<64, 133>; // n x 64 x i1 vector value
+
+def nxv1i8 : ValueType<8, 134>; // n x 1 x i8 vector value
+def nxv2i8 : ValueType<16, 135>; // n x 2 x i8 vector value
+def nxv4i8 : ValueType<32, 136>; // n x 4 x i8 vector value
+def nxv8i8 : ValueType<64, 137>; // n x 8 x i8 vector value
+def nxv16i8 : ValueType<128, 138>; // n x 16 x i8 vector value
+def nxv32i8 : ValueType<256, 139>; // n x 32 x i8 vector value
+def nxv64i8 : ValueType<512, 140>; // n x 64 x i8 vector value
+
+def nxv1i16 : ValueType<16, 141>; // n x 1 x i16 vector value
+def nxv2i16 : ValueType<32, 142>; // n x 2 x i16 vector value
+def nxv4i16 : ValueType<64, 143>; // n x 4 x i16 vector value
+def nxv8i16 : ValueType<128, 144>; // n x 8 x i16 vector value
+def nxv16i16 : ValueType<256, 145>; // n x 16 x i16 vector value
+def nxv32i16 : ValueType<512, 146>; // n x 32 x i16 vector value
+
+def nxv1i32 : ValueType<32, 147>; // n x 1 x i32 vector value
+def nxv2i32 : ValueType<64, 148>; // n x 2 x i32 vector value
+def nxv4i32 : ValueType<128, 149>; // n x 4 x i32 vector value
+def nxv8i32 : ValueType<256, 150>; // n x 8 x i32 vector value
+def nxv16i32 : ValueType<512, 151>; // n x 16 x i32 vector value
+def nxv32i32 : ValueType<1024, 152>; // n x 32 x i32 vector value
+
+def nxv1i64 : ValueType<64, 153>; // n x 1 x i64 vector value
+def nxv2i64 : ValueType<128, 154>; // n x 2 x i64 vector value
+def nxv4i64 : ValueType<256, 155>; // n x 4 x i64 vector value
+def nxv8i64 : ValueType<512, 156>; // n x 8 x i64 vector value
+def nxv16i64 : ValueType<1024, 157>; // n x 16 x i64 vector value
+def nxv32i64 : ValueType<2048, 158>; // n x 32 x i64 vector value
+
+def nxv1f16 : ValueType<16, 159>; // n x 1 x f16 vector value
+def nxv2f16 : ValueType<32, 160>; // n x 2 x f16 vector value
+def nxv4f16 : ValueType<64, 161>; // n x 4 x f16 vector value
+def nxv8f16 : ValueType<128, 162>; // n x 8 x f16 vector value
+def nxv16f16 : ValueType<256, 163>; // n x 16 x f16 vector value
+def nxv32f16 : ValueType<512, 164>; // n x 32 x f16 vector value
+
+def nxv1bf16 : ValueType<16, 165>; // n x 1 x bf16 vector value
+def nxv2bf16 : ValueType<32, 166>; // n x 2 x bf16 vector value
+def nxv4bf16 : ValueType<64, 167>; // n x 4 x bf16 vector value
+def nxv8bf16 : ValueType<128, 168>; // n x 8 x bf16 vector value
+def nxv16bf16 : ValueType<256, 169>; // n x 16 x bf16 vector value
+def nxv32bf16 : ValueType<512, 170>; // n x 32 x bf16 vector value
+
+def nxv1f32 : ValueType<32, 171>; // n x 1 x f32 vector value
+def nxv2f32 : ValueType<64, 172>; // n x 2 x f32 vector value
+def nxv4f32 : ValueType<128, 173>; // n x 4 x f32 vector value
+def nxv8f32 : ValueType<256, 174>; // n x 8 x f32 vector value
+def nxv16f32 : ValueType<512, 175>; // n x 16 x f32 vector value
+
+def nxv1f64 : ValueType<64, 176>; // n x 1 x f64 vector value
+def nxv2f64 : ValueType<128, 177>; // n x 2 x f64 vector value
+def nxv4f64 : ValueType<256, 178>; // n x 4 x f64 vector value
+def nxv8f64 : ValueType<512, 179>; // n x 8 x f64 vector value
+
+def x86mmx : ValueType<64, 180>; // X86 MMX value
+def FlagVT : ValueType<0, 181>; // Pre-RA sched glue
+def isVoid : ValueType<0, 182>; // Produces no value
+def untyped : ValueType<8, 183>; // Produces an untyped value
+def funcref : ValueType<0, 184>; // WebAssembly's funcref type
+def externref : ValueType<0, 185>; // WebAssembly's externref type
+def x86amx : ValueType<8192, 186>; // X86 AMX value
+def i64x8 : ValueType<512, 187>; // 8 Consecutive GPRs (AArch64)
def token : ValueType<0, 248>; // TokenTy
def MetadataVT : ValueType<0, 249>; // Metadata
diff --git a/llvm/include/llvm/IR/Intrinsics.td b/llvm/include/llvm/IR/Intrinsics.td
index 64d186c508ce8..e8fb5c4aef191 100644
--- a/llvm/include/llvm/IR/Intrinsics.td
+++ b/llvm/include/llvm/IR/Intrinsics.td
@@ -281,6 +281,7 @@ def llvm_v128i1_ty : LLVMType<v128i1>; // 128 x i1
def llvm_v256i1_ty : LLVMType<v256i1>; // 256 x i1
def llvm_v512i1_ty : LLVMType<v512i1>; // 512 x i1
def llvm_v1024i1_ty : LLVMType<v1024i1>; //1024 x i1
+def llvm_v2048i1_ty : LLVMType<v2048i1>; //2048 x i1
def llvm_v1i8_ty : LLVMType<v1i8>; // 1 x i8
def llvm_v2i8_ty : LLVMType<v2i8>; // 2 x i8
diff --git a/llvm/include/llvm/Support/MachineValueType.h b/llvm/include/llvm/Support/MachineValueType.h
index 3e263a7739532..1fe4128516adc 100644
--- a/llvm/include/llvm/Support/MachineValueType.h
+++ b/llvm/include/llvm/Support/MachineValueType.h
@@ -74,118 +74,119 @@ namespace llvm {
v256i1 = 25, // 256 x i1
v512i1 = 26, // 512 x i1
v1024i1 = 27, // 1024 x i1
-
- v128i2 = 28, // 128 x i2
- v256i2 = 29, // 256 x i2
-
- v64i4 = 30, // 64 x i4
- v128i4 = 31, // 128 x i4
-
- v1i8 = 32, // 1 x i8
- v2i8 = 33, // 2 x i8
- v4i8 = 34, // 4 x i8
- v8i8 = 35, // 8 x i8
- v16i8 = 36, // 16 x i8
- v32i8 = 37, // 32 x i8
- v64i8 = 38, // 64 x i8
- v128i8 = 39, // 128 x i8
- v256i8 = 40, // 256 x i8
- v512i8 = 41, // 512 x i8
- v1024i8 = 42, // 1024 x i8
-
- v1i16 = 43, // 1 x i16
- v2i16 = 44, // 2 x i16
- v3i16 = 45, // 3 x i16
- v4i16 = 46, // 4 x i16
- v8i16 = 47, // 8 x i16
- v16i16 = 48, // 16 x i16
- v32i16 = 49, // 32 x i16
- v64i16 = 50, // 64 x i16
- v128i16 = 51, // 128 x i16
- v256i16 = 52, // 256 x i16
- v512i16 = 53, // 512 x i16
-
- v1i32 = 54, // 1 x i32
- v2i32 = 55, // 2 x i32
- v3i32 = 56, // 3 x i32
- v4i32 = 57, // 4 x i32
- v5i32 = 58, // 5 x i32
- v6i32 = 59, // 6 x i32
- v7i32 = 60, // 7 x i32
- v8i32 = 61, // 8 x i32
- v16i32 = 62, // 16 x i32
- v32i32 = 63, // 32 x i32
- v64i32 = 64, // 64 x i32
- v128i32 = 65, // 128 x i32
- v256i32 = 66, // 256 x i32
- v512i32 = 67, // 512 x i32
- v1024i32 = 68, // 1024 x i32
- v2048i32 = 69, // 2048 x i32
-
- v1i64 = 70, // 1 x i64
- v2i64 = 71, // 2 x i64
- v3i64 = 72, // 3 x i64
- v4i64 = 73, // 4 x i64
- v8i64 = 74, // 8 x i64
- v16i64 = 75, // 16 x i64
- v32i64 = 76, // 32 x i64
- v64i64 = 77, // 64 x i64
- v128i64 = 78, // 128 x i64
- v256i64 = 79, // 256 x i64
-
- v1i128 = 80, // 1 x i128
+ v2048i1 = 28, // 2048 x i1
+
+ v128i2 = 29, // 128 x i2
+ v256i2 = 30, // 256 x i2
+
+ v64i4 = 31, // 64 x i4
+ v128i4 = 32, // 128 x i4
+
+ v1i8 = 33, // 1 x i8
+ v2i8 = 34, // 2 x i8
+ v4i8 = 35, // 4 x i8
+ v8i8 = 36, // 8 x i8
+ v16i8 = 37, // 16 x i8
+ v32i8 = 38, // 32 x i8
+ v64i8 = 39, // 64 x i8
+ v128i8 = 40, // 128 x i8
+ v256i8 = 41, // 256 x i8
+ v512i8 = 42, // 512 x i8
+ v1024i8 = 43, // 1024 x i8
+
+ v1i16 = 44, // 1 x i16
+ v2i16 = 45, // 2 x i16
+ v3i16 = 46, // 3 x i16
+ v4i16 = 47, // 4 x i16
+ v8i16 = 48, // 8 x i16
+ v16i16 = 49, // 16 x i16
+ v32i16 = 50, // 32 x i16
+ v64i16 = 51, // 64 x i16
+ v128i16 = 52, // 128 x i16
+ v256i16 = 53, // 256 x i16
+ v512i16 = 54, // 512 x i16
+
+ v1i32 = 55, // 1 x i32
+ v2i32 = 56, // 2 x i32
+ v3i32 = 57, // 3 x i32
+ v4i32 = 58, // 4 x i32
+ v5i32 = 59, // 5 x i32
+ v6i32 = 60, // 6 x i32
+ v7i32 = 61, // 7 x i32
+ v8i32 = 62, // 8 x i32
+ v16i32 = 63, // 16 x i32
+ v32i32 = 64, // 32 x i32
+ v64i32 = 65, // 64 x i32
+ v128i32 = 66, // 128 x i32
+ v256i32 = 67, // 256 x i32
+ v512i32 = 68, // 512 x i32
+ v1024i32 = 69, // 1024 x i32
+ v2048i32 = 70, // 2048 x i32
+
+ v1i64 = 71, // 1 x i64
+ v2i64 = 72, // 2 x i64
+ v3i64 = 73, // 3 x i64
+ v4i64 = 74, // 4 x i64
+ v8i64 = 75, // 8 x i64
+ v16i64 = 76, // 16 x i64
+ v32i64 = 77, // 32 x i64
+ v64i64 = 78, // 64 x i64
+ v128i64 = 79, // 128 x i64
+ v256i64 = 80, // 256 x i64
+
+ v1i128 = 81, // 1 x i128
FIRST_INTEGER_FIXEDLEN_VECTOR_VALUETYPE = v1i1,
LAST_INTEGER_FIXEDLEN_VECTOR_VALUETYPE = v1i128,
- v1f16 = 81, // 1 x f16
- v2f16 = 82, // 2 x f16
- v3f16 = 83, // 3 x f16
- v4f16 = 84, // 4 x f16
- v8f16 = 85, // 8 x f16
- v16f16 = 86, // 16 x f16
- v32f16 = 87, // 32 x f16
- v64f16 = 88, // 64 x f16
- v128f16 = 89, // 128 x f16
- v256f16 = 90, // 256 x f16
- v512f16 = 91, // 512 x f16
-
- v2bf16 = 92, // 2 x bf16
- v3bf16 = 93, // 3 x bf16
- v4bf16 = 94, // 4 x bf16
- v8bf16 = 95, // 8 x bf16
- v16bf16 = 96, // 16 x bf16
- v32bf16 = 97, // 32 x bf16
- v64bf16 = 98, // 64 x bf16
- v128bf16 = 99, // 128 x bf16
-
- v1f32 = 100, // 1 x f32
- v2f32 = 101, // 2 x f32
- v3f32 = 102, // 3 x f32
- v4f32 = 103, // 4 x f32
- v5f32 = 104, // 5 x f32
- v6f32 = 105, // 6 x f32
- v7f32 = 106, // 7 x f32
- v8f32 = 107, // 8 x f32
- v16f32 = 108, // 16 x f32
- v32f32 = 109, // 32 x f32
- v64f32 = 110, // 64 x f32
- v128f32 = 111, // 128 x f32
- v256f32 = 112, // 256 x f32
- v512f32 = 113, // 512 x f32
- v1024f32 = 114, // 1024 x f32
- v2048f32 = 115, // 2048 x f32
-
- v1f64 = 116, // 1 x f64
- v2f64 = 117, // 2 x f64
- v3f64 = 118, // 3 x f64
- v4f64 = 119, // 4 x f64
- v8f64 = 120, // 8 x f64
- v16f64 = 121, // 16 x f64
- v32f64 = 122, // 32 x f64
- v64f64 = 123, // 64 x f64
- v128f64 = 124, // 128 x f64
- v256f64 = 125, // 256 x f64
+ v1f16 = 82, // 1 x f16
+ v2f16 = 83, // 2 x f16
+ v3f16 = 84, // 3 x f16
+ v4f16 = 85, // 4 x f16
+ v8f16 = 86, // 8 x f16
+ v16f16 = 87, // 16 x f16
+ v32f16 = 88, // 32 x f16
+ v64f16 = 89, // 64 x f16
+ v128f16 = 90, // 128 x f16
+ v256f16 = 91, // 256 x f16
+ v512f16 = 92, // 512 x f16
+
+ v2bf16 = 93, // 2 x bf16
+ v3bf16 = 94, // 3 x bf16
+ v4bf16 = 95, // 4 x bf16
+ v8bf16 = 96, // 8 x bf16
+ v16bf16 = 97, // 16 x bf16
+ v32bf16 = 98, // 32 x bf16
+ v64bf16 = 99, // 64 x bf16
+ v128bf16 = 100, // 128 x bf16
+
+ v1f32 = 101, // 1 x f32
+ v2f32 = 102, // 2 x f32
+ v3f32 = 103, // 3 x f32
+ v4f32 = 104, // 4 x f32
+ v5f32 = 105, // 5 x f32
+ v6f32 = 106, // 6 x f32
+ v7f32 = 107, // 7 x f32
+ v8f32 = 108, // 8 x f32
+ v16f32 = 109, // 16 x f32
+ v32f32 = 110, // 32 x f32
+ v64f32 = 111, // 64 x f32
+ v128f32 = 112, // 128 x f32
+ v256f32 = 113, // 256 x f32
+ v512f32 = 114, // 512 x f32
+ v1024f32 = 115, // 1024 x f32
+ v2048f32 = 116, // 2048 x f32
+
+ v1f64 = 117, // 1 x f64
+ v2f64 = 118, // 2 x f64
+ v3f64 = 119, // 3 x f64
+ v4f64 = 120, // 4 x f64
+ v8f64 = 121, // 8 x f64
+ v16f64 = 122, // 16 x f64
+ v32f64 = 123, // 32 x f64
+ v64f64 = 124, // 64 x f64
+ v128f64 = 125, // 128 x f64
+ v256f64 = 126, // 256 x f64
FIRST_FP_FIXEDLEN_VECTOR_VALUETYPE = v1f16,
LAST_FP_FIXEDLEN_VECTOR_VALUETYPE = v256f64,
@@ -193,70 +194,70 @@ namespace llvm {
FIRST_FIXEDLEN_VECTOR_VALUETYPE = v1i1,
LAST_FIXEDLEN_VECTOR_VALUETYPE = v256f64,
- nxv1i1 = 126, // n x 1 x i1
- nxv2i1 = 127, // n x 2 x i1
- nxv4i1 = 128, // n x 4 x i1
- nxv8i1 = 129, // n x 8 x i1
- nxv16i1 = 130, // n x 16 x i1
- nxv32i1 = 131, // n x 32 x i1
- nxv64i1 = 132, // n x 64 x i1
-
- nxv1i8 = 133, // n x 1 x i8
- nxv2i8 = 134, // n x 2 x i8
- nxv4i8 = 135, // n x 4 x i8
- nxv8i8 = 136, // n x 8 x i8
- nxv16i8 = 137, // n x 16 x i8
- nxv32i8 = 138, // n x 32 x i8
- nxv64i8 = 139, // n x 64 x i8
-
- nxv1i16 = 140, // n x 1 x i16
- nxv2i16 = 141, // n x 2 x i16
- nxv4i16 = 142, // n x 4 x i16
- nxv8i16 = 143, // n x 8 x i16
- nxv16i16 = 144, // n x 16 x i16
- nxv32i16 = 145, // n x 32 x i16
-
- nxv1i32 = 146, // n x 1 x i32
- nxv2i32 = 147, // n x 2 x i32
- nxv4i32 = 148, // n x 4 x i32
- nxv8i32 = 149, // n x 8 x i32
- nxv16i32 = 150, // n x 16 x i32
- nxv32i32 = 151, // n x 32 x i32
-
- nxv1i64 = 152, // n x 1 x i64
- nxv2i64 = 153, // n x 2 x i64
- nxv4i64 = 154, // n x 4 x i64
- nxv8i64 = 155, // n x 8 x i64
- nxv16i64 = 156, // n x 16 x i64
- nxv32i64 = 157, // n x 32 x i64
+ nxv1i1 = 127, // n x 1 x i1
+ nxv2i1 = 128, // n x 2 x i1
+ nxv4i1 = 129, // n x 4 x i1
+ nxv8i1 = 130, // n x 8 x i1
+ nxv16i1 = 131, // n x 16 x i1
+ nxv32i1 = 132, // n x 32 x i1
+ nxv64i1 = 133, // n x 64 x i1
+
+ nxv1i8 = 134, // n x 1 x i8
+ nxv2i8 = 135, // n x 2 x i8
+ nxv4i8 = 136, // n x 4 x i8
+ nxv8i8 = 137, // n x 8 x i8
+ nxv16i8 = 138, // n x 16 x i8
+ nxv32i8 = 139, // n x 32 x i8
+ nxv64i8 = 140, // n x 64 x i8
+
+ nxv1i16 = 141, // n x 1 x i16
+ nxv2i16 = 142, // n x 2 x i16
+ nxv4i16 = 143, // n x 4 x i16
+ nxv8i16 = 144, // n x 8 x i16
+ nxv16i16 = 145, // n x 16 x i16
+ nxv32i16 = 146, // n x 32 x i16
+
+ nxv1i32 = 147, // n x 1 x i32
+ nxv2i32 = 148, // n x 2 x i32
+ nxv4i32 = 149, // n x 4 x i32
+ nxv8i32 = 150, // n x 8 x i32
+ nxv16i32 = 151, // n x 16 x i32
+ nxv32i32 = 152, // n x 32 x i32
+
+ nxv1i64 = 153, // n x 1 x i64
+ nxv2i64 = 154, // n x 2 x i64
+ nxv4i64 = 155, // n x 4 x i64
+ nxv8i64 = 156, // n x 8 x i64
+ nxv16i64 = 157, // n x 16 x i64
+ nxv32i64 = 158, // n x 32 x i64
FIRST_INTEGER_SCALABLE_VECTOR_VALUETYPE = nxv1i1,
LAST_INTEGER_SCALABLE_VECTOR_VALUETYPE = nxv32i64,
- nxv1f16 = 158, // n x 1 x f16
- nxv2f16 = 159, // n x 2 x f16
- nxv4f16 = 160, // n x 4 x f16
- nxv8f16 = 161, // n x 8 x f16
- nxv16f16 = 162, // n x 16 x f16
- nxv32f16 = 163, // n x 32 x f16
-
- nxv1bf16 = 164, // n x 1 x bf16
- nxv2bf16 = 165, // n x 2 x bf16
- nxv4bf16 = 166, // n x 4 x bf16
- nxv8bf16 = 167, // n x 8 x bf16
- nxv16bf16 = 168, // n x 16 x bf16
- nxv32bf16 = 169, // n x 32 x bf16
-
- nxv1f32 = 170, // n x 1 x f32
- nxv2f32 = 171, // n x 2 x f32
- nxv4f32 = 172, // n x 4 x f32
- nxv8f32 = 173, // n x 8 x f32
- nxv16f32 = 174, // n x 16 x f32
-
- nxv1f64 = 175, // n x 1 x f64
- nxv2f64 = 176, // n x 2 x f64
- nxv4f64 = 177, // n x 4 x f64
- nxv8f64 = 178, // n x 8 x f64
+ nxv1f16 = 159, // n x 1 x f16
+ nxv2f16 = 160, // n x 2 x f16
+ nxv4f16 = 161, // n x 4 x f16
+ nxv8f16 = 162, // n x 8 x f16
+ nxv16f16 = 163, // n x 16 x f16
+ nxv32f16 = 164, // n x 32 x f16
+
+ nxv1bf16 = 165, // n x 1 x bf16
+ nxv2bf16 = 166, // n x 2 x bf16
+ nxv4bf16 = 167, // n x 4 x bf16
+ nxv8bf16 = 168, // n x 8 x bf16
+ nxv16bf16 = 169, // n x 16 x bf16
+ nxv32bf16 = 170, // n x 32 x bf16
+
+ nxv1f32 = 171, // n x 1 x f32
+ nxv2f32 = 172, // n x 2 x f32
+ nxv4f32 = 173, // n x 4 x f32
+ nxv8f32 = 174, // n x 8 x f32
+ nxv16f32 = 175, // n x 16 x f32
+
+ nxv1f64 = 176, // n x 1 x f64
+ nxv2f64 = 177, // n x 2 x f64
+ nxv4f64 = 178, // n x 4 x f64
+ nxv8f64 = 179, // n x 8 x f64
FIRST_FP_SCALABLE_VECTOR_VALUETYPE = nxv1f16,
LAST_FP_SCALABLE_VECTOR_VALUETYPE = nxv8f64,
@@ -267,20 +268,20 @@ namespace llvm {
FIRST_VECTOR_VALUETYPE = v1i1,
LAST_VECTOR_VALUETYPE = nxv8f64,
- x86mmx = 179, // This is an X86 MMX value
+ x86mmx = 180, // This is an X86 MMX value
- Glue = 180, // This glues nodes together during pre-RA sched
+ Glue = 181, // This glues nodes together during pre-RA sched
- isVoid = 181, // This has no value
+ isVoid = 182, // This has no value
- Untyped = 182, // This value takes a register, but has
+ Untyped = 183, // This value takes a register, but has
// unspecified type. The register class
// will be determined by the opcode.
- funcref = 183, // WebAssembly's funcref type
- externref = 184, // WebAssembly's externref type
- x86amx = 185, // This is an X86 AMX value
- i64x8 = 186, // 8 Consecutive GPRs (AArch64)
+ funcref = 184, // WebAssembly's funcref type
+ externref = 185, // WebAssembly's externref type
+ x86amx = 186, // This is an X86 AMX value
+ i64x8 = 187, // 8 Consecutive GPRs (AArch64)
FIRST_VALUETYPE = 1, // This is always the beginning of the list.
LAST_VALUETYPE = i64x8, // This always remains at the end of the list.
@@ -456,7 +457,8 @@ namespace llvm {
return (SimpleTy == MVT::v256i8 || SimpleTy == MVT::v128i16 ||
SimpleTy == MVT::v64i32 || SimpleTy == MVT::v32i64 ||
SimpleTy == MVT::v128f16 || SimpleTy == MVT::v64f32 ||
- SimpleTy == MVT::v32f64 || SimpleTy == MVT::v128bf16);
+ SimpleTy == MVT::v32f64 || SimpleTy == MVT::v128bf16 ||
+ SimpleTy == MVT::v2048i1);
}
/// Return true if this is an overloaded type for TableGen.
@@ -544,6 +546,7 @@ namespace llvm {
case v256i1:
case v512i1:
case v1024i1:
+ case v2048i1:
case nxv1i1:
case nxv2i1:
case nxv4i1:
@@ -704,6 +707,7 @@ namespace llvm {
switch (SimpleTy) {
default:
llvm_unreachable("Not a vector MVT!");
+ case v2048i1:
case v2048i32:
case v2048f32: return 2048;
case v1024i1:
@@ -1054,6 +1058,7 @@ namespace llvm {
case v16f64: return TypeSize::Fixed(1024);
case nxv32i32:
case nxv16i64: return TypeSize::Scalable(1024);
+ case v2048i1:
case v256i8:
case v128i16:
case v64i32:
@@ -1239,6 +1244,7 @@ namespace llvm {
if (NumElements == 256) return MVT::v256i1;
if (NumElements == 512) return MVT::v512i1;
if (NumElements == 1024) return MVT::v1024i1;
+ if (NumElements == 2048) return MVT::v2048i1;
break;
case MVT::i2:
if (NumElements == 128) return MVT::v128i2;
diff --git a/llvm/lib/CodeGen/ValueTypes.cpp b/llvm/lib/CodeGen/ValueTypes.cpp
index 1bc03f0dfd833..cea97a30828ef 100644
--- a/llvm/lib/CodeGen/ValueTypes.cpp
+++ b/llvm/lib/CodeGen/ValueTypes.cpp
@@ -232,6 +232,8 @@ Type *EVT::getTypeForEVT(LLVMContext &Context) const {
return FixedVectorType::get(Type::getInt1Ty(Context), 512);
case MVT::v1024i1:
return FixedVectorType::get(Type::getInt1Ty(Context), 1024);
+ case MVT::v2048i1:
+ return FixedVectorType::get(Type::getInt1Ty(Context), 2048);
case MVT::v128i2:
return FixedVectorType::get(Type::getIntNTy(Context, 2), 128);
case MVT::v256i2:
diff --git a/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp b/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
index 915f689ac688c..e7f7c0cd32ed8 100644
--- a/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
+++ b/llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
@@ -29,7 +29,7 @@
using namespace llvm;
-DEFINE_PPC_REGCLASSES;
+DEFINE_PPC_REGCLASSES
// Evaluate an expression containing condition register
// or condition register field symbols. Returns positive
@@ -291,6 +291,26 @@ struct PPCOperand : public MCParsedAsmOperand {
return (unsigned) Imm.Val;
}
+ unsigned getDMRROWReg() const {
+ assert(isDMRROWRegNumber() && "Invalid access!");
+ return (unsigned)Imm.Val;
+ }
+
+ unsigned getDMRROWpReg() const {
+ assert(isDMRROWpRegNumber() && "Invalid access!");
+ return (unsigned)Imm.Val;
+ }
+
+ unsigned getDMRReg() const {
+ assert(isDMRRegNumber() && "Invalid access!");
+ return (unsigned)Imm.Val;
+ }
+
+ unsigned getDMRpReg() const {
+ assert(isDMRpRegNumber() && "Invalid access!");
+ return (unsigned)Imm.Val;
+ }
+
unsigned getVSRpEvenReg() const {
assert(isVSRpEvenRegNumber() && "Invalid access!");
return (unsigned) Imm.Val >> 1;
@@ -391,6 +411,18 @@ struct PPCOperand : public MCParsedAsmOperand {
bool isACCRegNumber() const {
return Kind == Immediate && isUInt<3>(getImm());
}
+ bool isDMRROWRegNumber() const {
+ return Kind == Immediate && isUInt<6>(getImm());
+ }
+ bool isDMRROWpRegNumber() const {
+ return Kind == Immediate && isUInt<5>(getImm());
+ }
+ bool isDMRRegNumber() const {
+ return Kind == Immediate && isUInt<3>(getImm());
+ }
+ bool isDMRpRegNumber() const {
+ return Kind == Immediate && isUInt<2>(getImm());
+ }
bool isVSRpEvenRegNumber() const {
return Kind == Immediate && isUInt<6>(getImm()) && ((getImm() & 1) == 0);
}
@@ -507,6 +539,36 @@ struct PPCOperand : public MCParsedAsmOperand {
Inst.addOperand(MCOperand::createReg(ACCRegs[getACCReg()]));
}
+ void addRegDMRROWRCOperands(MCInst &Inst, unsigned N) const {
+ assert(N == 1 && "Invalid number of operands!");
+ Inst.addOperand(MCOperand::createReg(DMRROWRegs[getDMRROWReg()]));
+ }
+
+ void addRegDMRROWpRCOperands(MCInst &Inst, unsigned N) const {
+ assert(N == 1 && "Invalid number of operands!");
+ Inst.addOperand(MCOperand::createReg(DMRROWpRegs[getDMRROWpReg()]));
+ }
+
+ void addRegDMRRCOperands(MCInst &Inst, unsigned N) const {
+ assert(N == 1 && "Invalid number of operands!");
+ Inst.addOperand(MCOperand::createReg(DMRRegs[getDMRReg()]));
+ }
+
+ void addRegDMRpRCOperands(MCInst &Inst, unsigned N) const {
+ assert(N == 1 && "Invalid number of operands!");
+ Inst.addOperand(MCOperand::createReg(DMRpRegs[getDMRpReg()]));
+ }
+
+ void addRegWACCRCOperands(MCInst &Inst, unsigned N) const {
+ assert(N == 1 && "Invalid number of operands!");
+ Inst.addOperand(MCOperand::createReg(WACCRegs[getACCReg()]));
+ }
+
+ void addRegWACC_HIRCOperands(MCInst &Inst, unsigned N) const {
+ assert(N == 1 && "Invalid number of operands!");
+ Inst.addOperand(MCOperand::createReg(WACC_HIRegs[getACCReg()]));
+ }
+
void addRegVSRpRCOperands(MCInst &Inst, unsigned N) const {
assert(N == 1 && "Invalid number of operands!");
Inst.addOperand(MCOperand::createReg(VSRpRegs[getVSRpEvenReg()]));
@@ -1218,6 +1280,27 @@ bool PPCAsmParser::MatchRegisterName(unsigned &RegNo, int64_t &IntVal) {
} else if (Name.startswith_insensitive("cr") &&
!Name.substr(2).getAsInteger(10, IntVal) && IntVal < 8) {
RegNo = CRRegs[IntVal];
+ } else if (Name.startswith_insensitive("acc") &&
+ !Name.substr(3).getAsInteger(10, IntVal) && IntVal < 8) {
+ RegNo = ACCRegs[IntVal];
+ } else if (Name.startswith_insensitive("wacc_hi") &&
+ !Name.substr(7).getAsInteger(10, IntVal) && IntVal < 8) {
+ RegNo = ACCRegs[IntVal];
+ } else if (Name.startswith_insensitive("wacc") &&
+ !Name.substr(4).getAsInteger(10, IntVal) && IntVal < 8) {
+ RegNo = WACCRegs[IntVal];
+ } else if (Name.startswith_insensitive("dmrrowp") &&
+ !Name.substr(7).getAsInteger(10, IntVal) && IntVal < 32) {
+ RegNo = DMRROWpRegs[IntVal];
+ } else if (Name.startswith_insensitive("dmrrow") &&
+ !Name.substr(6).getAsInteger(10, IntVal) && IntVal < 64) {
+ RegNo = DMRROWRegs[IntVal];
+ } else if (Name.startswith_insensitive("dmrp") &&
+ !Name.substr(4).getAsInteger(10, IntVal) && IntVal < 4) {
+ RegNo = DMRROWpRegs[IntVal];
+ } else if (Name.startswith_insensitive("dmr") &&
+ !Name.substr(3).getAsInteger(10, IntVal) && IntVal < 8) {
+ RegNo = DMRRegs[IntVal];
} else
return true;
getParser().Lex();
diff --git a/llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp b/llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp
index d3d720054f16a..21fee2441f32a 100644
--- a/llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp
+++ b/llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp
@@ -17,7 +17,7 @@
using namespace llvm;
-DEFINE_PPC_REGCLASSES;
+DEFINE_PPC_REGCLASSES
#define DEBUG_TYPE "ppc-disassembler"
@@ -187,6 +187,45 @@ static DecodeStatus DecodeACCRCRegisterClass(MCInst &Inst, uint64_t RegNo,
return decodeRegisterClass(Inst, RegNo, ACCRegs);
}
+static DecodeStatus DecodeWACCRCRegisterClass(MCInst &Inst, uint64_t RegNo,
+ uint64_t Address,
+ const void *Decoder) {
+ return decodeRegisterClass(Inst, RegNo, WACCRegs);
+}
+
+static DecodeStatus DecodeWACC_HIRCRegisterClass(MCInst &Inst, uint64_t RegNo,
+ uint64_t Address,
+ const void *Decoder) {
+ return decodeRegisterClass(Inst, RegNo, WACC_HIRegs);
+}
+
+// TODO: Make this function static when the register class is used by a new
+// instruction.
+DecodeStatus DecodeDMRROWRCRegisterClass(MCInst &Inst, uint64_t RegNo,
+ uint64_t Address,
+ const void *Decoder) {
+ return decodeRegisterClass(Inst, RegNo, DMRROWRegs);
+}
+
+static DecodeStatus DecodeDMRROWpRCRegisterClass(MCInst &Inst, uint64_t RegNo,
+ uint64_t Address,
+ const void *Decoder) {
+ return decodeRegisterClass(Inst, RegNo, DMRROWpRegs);
+}
+
+static DecodeStatus DecodeDMRRCRegisterClass(MCInst &Inst, uint64_t RegNo,
+ uint64_t Address,
+ const void *Decoder) {
+ return decodeRegisterClass(Inst, RegNo, DMRRegs);
+}
+
+// TODO: Make this function static when the register class is used by a new
+// instruction.
+DecodeStatus DecodeDMRpRCRegisterClass(MCInst &Inst, uint64_t RegNo,
+ uint64_t Address, const void *Decoder) {
+ return decodeRegisterClass(Inst, RegNo, DMRpRegs);
+}
+
static DecodeStatus DecodeVSRpRCRegisterClass(MCInst &Inst, uint64_t RegNo,
uint64_t Address,
const MCDisassembler *Decoder) {
diff --git a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h
index 3ca6f394f60b6..e4521aebad7ef 100644
--- a/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h
+++ b/llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h
@@ -136,6 +136,17 @@ static inline bool isRunOfOnes64(uint64_t Val, unsigned &MB, unsigned &ME) {
X##22, X##23, X##24, X##25, X##26, X##27, X##28, X##29, X##30, X##31 \
}
+#define PPC_REGS0_63(X) \
+ { \
+ X##0, X##1, X##2, X##3, X##4, X##5, X##6, X##7, X##8, X##9, X##10, X##11, \
+ X##12, X##13, X##14, X##15, X##16, X##17, X##18, X##19, X##20, X##21, \
+ X##22, X##23, X##24, X##25, X##26, X##27, X##28, X##29, X##30, X##31, \
+ X##32, X##33, X##34, X##35, X##36, X##37, X##38, X##39, X##40, X##41, \
+ X##42, X##43, X##44, X##45, X##46, X##47, X##48, X##49, X##50, X##51, \
+ X##52, X##53, X##54, X##55, X##56, X##57, X##58, X##59, X##60, X##61, \
+ X##62, X##63 \
+ }
+
#define PPC_REGS_NO0_31(Z, X) \
{ \
Z, X##1, X##2, X##3, X##4, X##5, X##6, X##7, X##8, X##9, X##10, X##11, \
@@ -155,6 +166,16 @@ static inline bool isRunOfOnes64(uint64_t Val, unsigned &MB, unsigned &ME) {
HI##28, HI##29, HI##30, HI##31 \
}
+#define PPC_REGS0_7(X) \
+ { \
+ X##0, X##1, X##2, X##3, X##4, X##5, X##6, X##7 \
+ }
+
+#define PPC_REGS0_3(X) \
+ { \
+ X##0, X##1, X##2, X##3 \
+ }
+
using llvm::MCPhysReg;
#define DEFINE_PPC_REGCLASSES \
@@ -185,5 +206,13 @@ using llvm::MCPhysReg;
PPC::CR6LT, PPC::CR6GT, PPC::CR6EQ, PPC::CR6UN, \
PPC::CR7LT, PPC::CR7GT, PPC::CR7EQ, PPC::CR7UN}; \
static const MCPhysReg CRRegs[8] = PPC_REGS0_7(PPC::CR); \
- static const MCPhysReg ACCRegs[8] = PPC_REGS0_7(PPC::ACC)
+ static const MCPhysReg ACCRegs[8] = PPC_REGS0_7(PPC::ACC); \
+ static const MCPhysReg WACCRegs[8] = PPC_REGS0_7(PPC::WACC); \
+ static const MCPhysReg WACC_HIRegs[8] = PPC_REGS0_7(PPC::WACC_HI); \
+ static const MCPhysReg DMRROWpRegs[32] = PPC_REGS0_31(PPC::DMRROWp); \
+ static const MCPhysReg DMRROWRegs[64] = PPC_REGS0_63(PPC::DMRROW); \
+ static const MCPhysReg DMRRegs[8] = PPC_REGS0_7(PPC::DMR); \
+ static const MCPhysReg DMRpRegs[4] = PPC_REGS0_3(PPC::DMRp);
+
+
#endif // LLVM_LIB_TARGET_POWERPC_MCTARGETDESC_PPCMCTARGETDESC_H
diff --git a/llvm/lib/Target/PowerPC/PPCInstrFuture.td b/llvm/lib/Target/PowerPC/PPCInstrFuture.td
new file mode 100644
index 0000000000000..63b77e46f01f4
--- /dev/null
+++ b/llvm/lib/Target/PowerPC/PPCInstrFuture.td
@@ -0,0 +1,14 @@
+//===-- PPCInstrFuture.td - Future Instruction Set --------*- tablegen -*-===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file describes the instructions introduced for the Future CPU.
+//
+//===----------------------------------------------------------------------===//
+
+
diff --git a/llvm/lib/Target/PowerPC/PPCInstrFutureMMA.td b/llvm/lib/Target/PowerPC/PPCInstrFutureMMA.td
new file mode 100644
index 0000000000000..4da2969857d55
--- /dev/null
+++ b/llvm/lib/Target/PowerPC/PPCInstrFutureMMA.td
@@ -0,0 +1,116 @@
+//===-- PPCInstrFutureMMA.td - Future Instruction Set ------*- tablegen -*-===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===----------------------------------------------------------------------===//
+//
+// This file describes the instructions introduced for the Future CPU for MMA.
+//
+//===----------------------------------------------------------------------===//
+
+class XX3Form_AT3_XABp5_P1<bits<6> opcode, bits<8> xo, dag OOL, dag IOL,
+ string asmstr, list<dag> pattern>
+ : I<opcode, OOL, IOL, asmstr, NoItinerary> {
+ bits<3> AT;
+ bits<5> XAp;
+ bits<5> XBp;
+ bits<1> P;
+
+ let Pattern = pattern;
+
+ let Inst{6-8} = AT{2-0};
+ let Inst{9-10} = 0;
+ let Inst{11-14} = XAp{3-0};
+ let Inst{15} = P;
+ let Inst{16-19} = XBp{3-0};
+ let Inst{20} = 0;
+ let Inst{21-28} = xo;
+ let Inst{29} = XAp{4};
+ let Inst{30} = XBp{4};
+ let Inst{31} = 0;
+}
+
+class XX2Form_AT3_XBp5_P2<bits<6> opcode, bits<9> xo, dag OOL, dag IOL,
+ string asmstr, list<dag> pattern>
+ : I<opcode, OOL, IOL, asmstr, NoItinerary> {
+ bits<3> AT;
+ bits<5> XBp;
+ bits<2> P;
+
+ let Pattern = pattern;
+
+ let Inst{6-8} = AT{2-0};
+ let Inst{9-14} = 0;
+ let Inst{15} = P{0};
+ let Inst{16-19} = XBp{3-0};
+ let Inst{20} = P{1};
+ let Inst{21-29} = xo;
+ let Inst{30} = XBp{4};
+ let Inst{31} = 0;
+}
+
+class XForm_ATB3<bits<6> opcode, bits<5> o, bits<10> xo, dag OOL, dag IOL,
+ string asmstr, list<dag> pattern>
+ : I <opcode, OOL, IOL, asmstr, NoItinerary> {
+ bits<3> AT;
+ bits<3> AB;
+
+ let Pattern = pattern;
+
+ let Inst{6-8} = AT{2-0};
+ let Inst{9-10} = 0;
+ let Inst{11-15} = o;
+ let Inst{16-18} = AB{2-0};
+ let Inst{19-20} = 0;
+ let Inst{21-30} = xo;
+ let Inst{31} = 0;
+}
+
+let Predicates = [IsISAFuture] in {
+ def DMXXEXTFDMR512 : XX3Form_AT3_XABp5_P1<60, 226,
+ (outs vsrprc:$XAp, vsrprc:$XBp),
+ (ins wacc:$AT),
+ "dmxxextfdmr512 $AT, $XAp, $XBp, 0", []> {
+ let P = 0;
+ }
+
+ def DMXXEXTFDMR512_HI : XX3Form_AT3_XABp5_P1<60, 226,
+ (outs vsrprc:$XAp, vsrprc:$XBp),
+ (ins wacc_hi:$AT),
+ "dmxxextfdmr512 $AT, $XAp, $XBp, 1", []> {
+ let P = 1;
+ }
+
+ def DMXXINSTFDMR512 : XX3Form_AT3_XABp5_P1<60, 234, (outs wacc:$AT),
+ (ins vsrprc:$XAp, vsrprc:$XBp),
+ "dmxxinstfdmr512 $AT, $XAp, $XBp, 0", []> {
+ let P = 0;
+ }
+
+ def DMXXINSTFDMR512_HI : XX3Form_AT3_XABp5_P1<60, 234, (outs wacc_hi:$AT),
+ (ins vsrprc:$XAp, vsrprc:$XBp),
+ "dmxxinstfdmr512 $AT, $XAp, $XBp, 1", []> {
+ let P = 1;
+ }
+
+ def DMXXEXTFDMR256 : XX2Form_AT3_XBp5_P2<60, 484, (outs vsrprc:$XBp),
+ (ins dmrrowp:$AT, u2imm:$P),
+ "dmxxextfdmr256 $AT, $XBp, $P", []>;
+
+ def DMXXINSTFDMR256 : XX2Form_AT3_XBp5_P2<60, 485, (outs dmrrowp:$AT),
+ (ins vsrprc:$XBp, u2imm:$P),
+ "dmxxinstfdmr256 $AT, $XBp, $P", []>;
+
+ def DMMR : XForm_ATB3<31, 6, 177, (outs dmr:$AT), (ins dmr:$AB),
+ "dmmr $AT, $AB", []>;
+
+ def DMXOR : XForm_ATB3<31, 7, 177, (outs dmr:$AT), (ins dmr:$ATi, dmr:$AB),
+ "dmxor $AT, $AB", []>,
+ RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
+
+ def DMSETDMRZ : XForm_AT3<31, 2, 177, (outs dmr:$AT), (ins),
+ "dmsetdmrz $AT", NoItinerary, []>;
+}
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.td b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
index ea4ef12bf21d2..8c8891b4b05cd 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -3278,6 +3278,8 @@ def : Pat<(not i1:$in),
// Prefixed instructions may require access to the above defs at a later
// time so we include this after the def.
include "PPCInstrP10.td"
+include "PPCInstrFutureMMA.td"
+include "PPCInstrFuture.td"
include "PPCInstrMMA.td"
// Patterns for arithmetic i1 operations.
diff --git a/llvm/lib/Target/PowerPC/PPCRegisterInfo.h b/llvm/lib/Target/PowerPC/PPCRegisterInfo.h
index aaa841fffa1b3..fea1a3afab1c2 100644
--- a/llvm/lib/Target/PowerPC/PPCRegisterInfo.h
+++ b/llvm/lib/Target/PowerPC/PPCRegisterInfo.h
@@ -184,7 +184,33 @@ class PPCRegisterInfo : public PPCGenRegisterInfo {
return RegName + 2;
}
return RegName + 1;
- case 'c': if (RegName[1] == 'r') return RegName + 2;
+ case 'c':
+ if (RegName[1] == 'r')
+ return RegName + 2;
+ break;
+ case 'w':
+ // For wacc and wacc_hi
+ if (RegName[1] == 'a' && RegName[2] == 'c' && RegName[3] == 'c') {
+ if (RegName[4] == '_')
+ return RegName + 7;
+ else
+ return RegName + 4;
+ }
+ break;
+ case 'd':
+ // For dmr, dmrp, dmrrow, dmrrowp
+ if (RegName[1] == 'm' && RegName[2] == 'r') {
+ if (RegName[3] == 'r' && RegName[4] == 'o' && RegName[5] == 'w' &&
+ RegName[6] == 'p')
+ return RegName + 7;
+ else if (RegName[3] == 'r' && RegName[4] == 'o' && RegName[5] == 'w')
+ return RegName + 6;
+ else if (RegName[3] == 'p')
+ return RegName + 4;
+ else
+ return RegName + 3;
+ }
+ break;
}
return RegName;
diff --git a/llvm/lib/Target/PowerPC/PPCRegisterInfo.td b/llvm/lib/Target/PowerPC/PPCRegisterInfo.td
index 49b26cd160608..32f8163a38828 100644
--- a/llvm/lib/Target/PowerPC/PPCRegisterInfo.td
+++ b/llvm/lib/Target/PowerPC/PPCRegisterInfo.td
@@ -446,6 +446,7 @@ def G8pRC :
}
include "PPCRegisterInfoMMA.td"
+include "PPCRegisterInfoDMR.td"
//===----------------------------------------------------------------------===//
// PowerPC Operand Definitions.
@@ -1013,3 +1014,48 @@ def acc : RegisterOperand<ACCRC> {
def uacc : RegisterOperand<UACCRC> {
let ParserMatchClass = PPCRegACCRCAsmOperand;
}
+
+// DMR Register Operands
+def PPCRegDMRROWRCAsmOperand : AsmOperandClass {
+ let Name = "RegDMRROWRC";
+ let PredicateMethod = "isDMRROWRegNumber";
+}
+
+def dmrrow : RegisterOperand<DMRROWRC> {
+ let ParserMatchClass = PPCRegDMRROWRCAsmOperand;
+}
+
+def PPCRegDMRROWpRCAsmOperand : AsmOperandClass {
+ let Name = "RegDMRROWpRC";
+ let PredicateMethod = "isDMRROWpRegNumber";
+}
+
+def dmrrowp : RegisterOperand<DMRROWpRC> {
+ let ParserMatchClass = PPCRegDMRROWpRCAsmOperand;
+}
+
+def wacc : RegisterOperand<WACCRC> {
+ let ParserMatchClass = PPCRegACCRCAsmOperand;
+}
+
+def wacc_hi : RegisterOperand<WACC_HIRC> {
+ let ParserMatchClass = PPCRegACCRCAsmOperand;
+}
+
+def PPCRegDMRRCAsmOperand : AsmOperandClass {
+ let Name = "RegDMRRC";
+ let PredicateMethod = "isDMRRegNumber";
+}
+
+def dmr : RegisterOperand<DMRRC> {
+ let ParserMatchClass = PPCRegDMRRCAsmOperand;
+}
+
+def PPCRegDMRpRCAsmOperand : AsmOperandClass {
+ let Name = "RegDMRpRC";
+ let PredicateMethod = "isDMRpRegNumber";
+}
+
+def dmrp : RegisterOperand<DMRpRC> {
+ let ParserMatchClass = PPCRegDMRpRCAsmOperand;
+}
diff --git a/llvm/lib/Target/PowerPC/PPCRegisterInfoDMR.td b/llvm/lib/Target/PowerPC/PPCRegisterInfoDMR.td
new file mode 100644
index 0000000000000..1c3e7621825bd
--- /dev/null
+++ b/llvm/lib/Target/PowerPC/PPCRegisterInfoDMR.td
@@ -0,0 +1,164 @@
+//===- PPCRegisterInfoDMR.td - The PowerPC Register File *- tablegen -*----===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// Register info specific to Power PC Dense Math Registers(DMR).
+//
+// Register classes in this file are related to the Dense Math Registers (DMR).
+// There are a total of 8 DMR registers numbered 0 to 7.
+// The 4
diff erent views of each DMR register.
+//
+// [ DMR0 ]
+// | WACC0 | WACC_HI0 |
+// | DMRROWp0 | DMRROWp1 | DMRROWp2 | DMRROWp3 |
+// |DMRROW0|DMRROW1|DMRROW2|DMRROW3|DMRROW4|DMRROW5|DMRROW6|DMRROW7|
+// [128bits|128bits|128bits|128bits|128bits|128bits|128bits|128bits]
+//
+// In addition to the above classes two consecutive DMR registers make a DMR
+// DMR pair (DMRp) that is 2048 bits.
+//===----------------------------------------------------------------------===//
+
+let Namespace = "PPC" in {
+def sub_dmrrow0 : SubRegIndex<128>;
+def sub_dmrrow1 : SubRegIndex<128, 128>;
+def sub_dmrrowp0 : SubRegIndex<256>;
+def sub_dmrrowp1 : SubRegIndex<256, 256>;
+def sub_wacc_lo : SubRegIndex<512>;
+def sub_wacc_hi : SubRegIndex<512, 512>;
+def sub_dmr0 : SubRegIndex<1024>;
+def sub_dmr1 : SubRegIndex<1024, 1024>;
+}
+
+// A single row in a DMR register.
+// There are 8 128 bit rows in each DMR register and 8 DMR registers so that
+// makes 64 DMRROW registers in total.
+class DMRROW<bits<6> num, string n> : PPCReg<n> {
+ let HWEncoding{5-0} = num;
+}
+
+// A consecutive pair of DMR row registers.
+class DMRROWp<bits<5> num, string n, list<Register> subregs> : PPCReg<n> {
+ let HWEncoding{4-0} = num;
+ let SubRegs = subregs;
+}
+
+// WACC - Wide ACC registers. Accumulator registers that are subregs of DMR.
+// These ACC registers no longer include VSR regs as subregs.
+class WACC<bits<3> num, string n, list<Register> subregs> : PPCReg<n> {
+ let HWEncoding{2-0} = num;
+ let SubRegs = subregs;
+}
+
+// High bits for the ACC registers.
+// When the ACC register is used these bits are ignored.
+// When the ACC register is the target, these bits are set to zero.
+class WACC_HI<bits<3> num, string n, list<Register> subregs> : PPCReg<n> {
+ let HWEncoding{2-0} = num;
+ let SubRegs = subregs;
+}
+
+class DMR<bits<3> num, string n, list<Register> subregs> : PPCReg<n> {
+ let HWEncoding{2-0} = num;
+ let SubRegs = subregs;
+}
+
+class DMRp<bits<2> num, string n, list<Register> subregs> : PPCReg<n> {
+ let HWEncoding{1-0} = num;
+ let SubRegs = subregs;
+}
+
+// The DMR Row type registers are the lowest level of registers and have no
+// subregs.
+foreach Index = 0-63 in {
+ def DMRROW#Index : DMRROW<Index, "dmrrow"#Index>, DwarfRegNum<[-1, -1]>;
+}
+
+// DMRROW pairs are consecutive pairs.
+// DMRROWp0 = DMRROW0, DMRROW1
+// DMRROWp1 = DMRROW2, DMRROW3
+// DMRROWp2 = DMRROW4, DMRROW5
+// etc...
+let SubRegIndices = [sub_dmrrow0, sub_dmrrow1] in {
+ foreach Index = 0-31 in {
+ def DMRROWp#Index : DMRROWp<Index, "dmrrowp"#Index,
+ [!cast<DMRROW>("DMRROW"#!mul(Index, 2)),
+ !cast<DMRROW>("DMRROW"#!add(!mul(Index, 2), 1))]>, DwarfRegNum<[-1, -1]>;
+ }
+}
+
+let SubRegIndices = [sub_dmrrowp0, sub_dmrrowp1] in {
+ // WACC0 = DMRROWp0, DMRROWp1
+ // WACC1 = DMRROWp4, DMRROWp5
+ // WACC2 = DMRROWp8, DMRROWp9
+ // etc...
+ foreach Index = 0-7 in {
+ def WACC#Index : WACC<Index, "wacc"#Index,
+ [!cast<DMRROWp>("DMRROWp"#!mul(Index, 4)),
+ !cast<DMRROWp>("DMRROWp"#!add(!mul(Index, 4), 1))]>, DwarfRegNum<[-1, -1]>;
+ }
+
+ // WACC_HI0 = DMRROWp2, DMRROWp3
+ // WACC_HI1 = DMRROWp6, DMRROWp7
+ // WACC_HI2 = DMRROWp10, DMRROWp11
+ // etc...
+ foreach Index = 0-7 in {
+ def WACC_HI#Index : WACC_HI<Index, "wacc_hi"#Index,
+ [!cast<DMRROWp>("DMRROWp"#!add(!mul(Index, 4), 2)),
+ !cast<DMRROWp>("DMRROWp"#!add(!mul(Index, 4), 3))]>, DwarfRegNum<[-1, -1]>;
+ }
+}
+
+// DMR0 = WACC0, WACC_HI0
+// DMR1 = WACC1, WACC_HI1
+// DMR2 = WACC2, WACC_HI2
+// etc...
+let SubRegIndices = [sub_wacc_lo, sub_wacc_hi] in {
+ foreach Index = 0-7 in {
+ def DMR#Index : DMR<Index, "dmr"#Index, [!cast<WACC>("WACC"#Index), !cast<WACC_HI>("WACC_HI"#Index)]>, DwarfRegNum<[-1, -1]>;
+ }
+}
+
+// DMRp0 = DMR0, DMR1
+// DMRp1 = DMR2, DMR3
+// DMRp2 = DMR4, DMR5
+// DMRp3 = DMR6, DMR7
+let SubRegIndices = [sub_dmr0, sub_dmr1] in {
+ def DMRp0 : DMRp<0, "dmrp0", [DMR0, DMR1]>, DwarfRegNum<[-1, -1]>;
+ def DMRp1 : DMRp<1, "dmrp1", [DMR2, DMR3]>, DwarfRegNum<[-1, -1]>;
+ def DMRp2 : DMRp<2, "dmrp2", [DMR4, DMR5]>, DwarfRegNum<[-1, -1]>;
+ def DMRp3 : DMRp<3, "dmrp3", [DMR6, DMR7]>, DwarfRegNum<[-1, -1]>;
+}
+
+def DMRROWRC : RegisterClass<"PPC", [v128i1], 128,
+ (add (sequence "DMRROW%u", 0, 63))> {
+ let Size = 128;
+}
+
+def DMRROWpRC : RegisterClass<"PPC", [v256i1], 128,
+ (add (sequence "DMRROWp%u", 0, 31))> {
+ let Size = 256;
+}
+
+def WACCRC : RegisterClass<"PPC", [v512i1], 128,
+ (add (sequence "WACC%u", 0, 7))> {
+ let Size = 512;
+}
+
+def WACC_HIRC : RegisterClass<"PPC", [v512i1], 128,
+ (add (sequence "WACC_HI%u", 0, 7))> {
+ let Size = 512;
+}
+
+def DMRRC : RegisterClass<"PPC", [v1024i1], 128,
+ (add (sequence "DMR%u", 0, 7))> {
+ let Size = 1024;
+}
+
+def DMRpRC : RegisterClass<"PPC", [v2048i1], 128,
+ (add DMRp0, DMRp1, DMRp2, DMRp3)> {
+ let Size = 2048;
+}
diff --git a/llvm/lib/Target/PowerPC/PPCScheduleP9.td b/llvm/lib/Target/PowerPC/PPCScheduleP9.td
index d350111717159..e9f4daa62de3c 100644
--- a/llvm/lib/Target/PowerPC/PPCScheduleP9.td
+++ b/llvm/lib/Target/PowerPC/PPCScheduleP9.td
@@ -38,10 +38,11 @@ def P9Model : SchedMachineModel {
let CompleteModel = 1;
- // Do not support SPE (Signal Processing Engine), prefixed instructions on
- // Power 9, paired vector mem ops, MMA, PC relative mem ops, or instructions
- // introduced in ISA 3.1.
- let UnsupportedFeatures = [HasSPE, PrefixInstrs, PairedVectorMemops, MMA,
+ // Do not support SPE (Signal Processing Engine) or prefixed instructions on
+ // Power 9, or MMA, or paired vector mem ops, or PC relative mem ops, or
+ // instructions introduced after ISA 3.0.
+ let UnsupportedFeatures = [HasSPE, PrefixInstrs, MMA,
+ PairedVectorMemops,
PCRelativeMemops, IsISA3_1, IsISAFuture];
}
diff --git a/llvm/test/CodeGen/PowerPC/future-check-features.ll b/llvm/test/CodeGen/PowerPC/future-check-features.ll
index 1dca4dafd5b64..f881119335d09 100644
--- a/llvm/test/CodeGen/PowerPC/future-check-features.ll
+++ b/llvm/test/CodeGen/PowerPC/future-check-features.ll
@@ -1,9 +1,19 @@
-; RUN: llc -mattr=pcrelative-memops,prefix-instrs,paired-vector-memops,mma,rop-protect,privileged \
+; RUN: llc -mattr=isa-future-instructions,pcrelative-memops,prefix-instrs \
+; RUN: -mattr=paired-vector-memops,mma,rop-protect,privileged \
; RUN: -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown \
; RUN: -ppc-asm-full-reg-names %s -o - 2>&1 | FileCheck %s
-; RUN: llc -mattr=pcrelative-memops,prefix-instrs,paired-vector-memops,mma,rop-protect,privileged \
+; RUN: llc -mattr=isa-future-instructions,pcrelative-memops,prefix-instrs \
+; RUN: -mattr=paired-vector-memops,mma,rop-protect,privileged \
; RUN: -verify-machineinstrs -mtriple=powerpc64-unknown-unknown \
; RUN: -ppc-asm-full-reg-names %s -o - 2>&1 | FileCheck %s
+; RUN: llc -mattr=isa-future-instructions,pcrelative-memops,prefix-instrs \
+; RUN: -mattr=paired-vector-memops,mma,rop-protect,privileged \
+; RUN: -verify-machineinstrs -mtriple=powerpc64-ibm-aix-xcoff \
+; RUN: -ppc-asm-full-reg-names %s -o - 2>&1 | FileCheck %s
+; RUN: llc -mattr=isa-future-instructions,pcrelative-memops,prefix-instrs \
+; RUN: -mattr=paired-vector-memops,mma,rop-protect,privileged \
+; RUN: -verify-machineinstrs -mtriple=powerpc-ibm-aix-xcoff \
+; RUN: -ppc-asm-full-reg-names %s -o - 2>&1 | FileCheck %s
define dso_local signext i32 @f() {
entry:
diff --git a/llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt b/llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt
new file mode 100644
index 0000000000000..87059b9e3c16c
--- /dev/null
+++ b/llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt
@@ -0,0 +1,41 @@
+# RUN: llvm-mc --disassemble %s -triple powerpc64-unknown-linux-gnu \
+# RUN: -mcpu=future | FileCheck %s
+
+# RUN: llvm-mc --disassemble %s -triple powerpc64-unknown-aix-gnu \
+# RUN: -mcpu=future | FileCheck %s
+
+# RUN: llvm-mc --disassemble %s -triple powerpc-unknown-aix-gnu \
+# RUN: -mcpu=future | FileCheck %s
+
+#CHECK: dmxxextfdmr512 1, 2, 34, 0
+0xf0 0x82 0x17 0x12
+
+#CHECK: dmxxextfdmr512 1, 2, 34, 1
+0xf0 0x83 0x17 0x12
+
+#CHECK: dmxxextfdmr256 3, 8, 0
+0xf1 0x80 0x47 0x90
+
+#CHECK: dmxxextfdmr256 3, 8, 3
+0xf1 0x81 0x4f 0x90
+
+#CHECK: dmxxinstfdmr512 1, 2, 34, 0
+0xf0 0x82 0x17 0x52
+
+#CHECK: dmxxinstfdmr512 1, 2, 34, 1
+0xf0 0x83 0x17 0x52
+
+#CHECK: dmxxinstfdmr256 3, 8, 0
+0xf1 0x80 0x47 0x94
+
+#CHECK: dmxxinstfdmr256 3, 8, 3
+0xf1 0x81 0x4f 0x94
+
+#CHECK: dmsetdmrz 3
+0x7d 0x82 0x01 0x62
+
+#CHECK: dmmr 4, 5
+0x7e 0x06 0xa1 0x62
+
+#CHECK: dmxor 6, 7
+0x7f 0x07 0xe1 0x62
diff --git a/llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt b/llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt
new file mode 100644
index 0000000000000..32dfcb28bf57c
--- /dev/null
+++ b/llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt
@@ -0,0 +1,35 @@
+# RUN: llvm-mc --disassemble %s -triple powerpc64le-unknown-unknown \
+# RUN: -mcpu=future | FileCheck %s
+
+#CHECK: dmxxextfdmr512 1, 2, 34, 0
+0x12 0x17 0x82 0xf0
+
+#CHECK: dmxxextfdmr512 1, 2, 34, 1
+0x12 0x17 0x83 0xf0
+
+#CHECK: dmxxextfdmr256 3, 8, 0
+0x90 0x47 0x80 0xf1
+
+#CHECK: dmxxextfdmr256 3, 8, 3
+0x90 0x4f 0x81 0xf1
+
+#CHECK: dmxxinstfdmr512 1, 2, 34, 0
+0x52 0x17 0x82 0xf0
+
+#CHECK: dmxxinstfdmr512 1, 2, 34, 1
+0x52 0x17 0x83 0xf0
+
+#CHECK: dmxxinstfdmr256 3, 8, 0
+0x94 0x47 0x80 0xf1
+
+#CHECK: dmxxinstfdmr256 3, 8, 3
+0x94 0x4f 0x81 0xf1
+
+#CHECK: dmsetdmrz 3
+0x62 0x01 0x82 0x7d
+
+#CHECK: dmmr 4, 5
+0x62 0xa1 0x06 0x7e
+
+#CHECK: dmxor 6, 7
+0x62 0xe1 0x07 0x7f
diff --git a/llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s b/llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s
new file mode 100644
index 0000000000000..2f7986f221c97
--- /dev/null
+++ b/llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s
@@ -0,0 +1,50 @@
+# RUN: llvm-mc -triple powerpc64-unknown-linux-gnu --show-encoding %s | \
+# RUN: FileCheck -check-prefix=CHECK-BE %s
+# RUN: llvm-mc -triple powerpc64le-unknown-linux-gnu --show-encoding %s | \
+# RUN: FileCheck -check-prefix=CHECK-LE %s
+# RUN: llvm-mc -triple powerpc-unknown-aix-gnu --show-encoding %s | \
+# RUN: FileCheck -check-prefix=CHECK-BE %s
+
+# CHECK-BE: dmxxextfdmr512 1, 2, 34, 0 # encoding: [0xf0,0x82,0x17,0x12]
+# CHECK-LE: dmxxextfdmr512 1, 2, 34, 0 # encoding: [0x12,0x17,0x82,0xf0]
+ dmxxextfdmr512 1, 2, 34, 0
+
+# CHECK-BE: dmxxextfdmr512 1, 2, 34, 1 # encoding: [0xf0,0x83,0x17,0x12]
+# CHECK-LE: dmxxextfdmr512 1, 2, 34, 1 # encoding: [0x12,0x17,0x83,0xf0]
+ dmxxextfdmr512 1, 2, 34, 1
+
+# CHECK-BE: dmxxextfdmr256 3, 8, 0 # encoding: [0xf1,0x80,0x47,0x90]
+# CHECK-LE: dmxxextfdmr256 3, 8, 0 # encoding: [0x90,0x47,0x80,0xf1]
+ dmxxextfdmr256 3, 8, 0
+
+# CHECK-BE: dmxxextfdmr256 3, 8, 3 # encoding: [0xf1,0x81,0x4f,0x90]
+# CHECK-LE: dmxxextfdmr256 3, 8, 3 # encoding: [0x90,0x4f,0x81,0xf1]
+ dmxxextfdmr256 3, 8, 3
+
+# CHECK-BE: dmxxinstfdmr512 1, 2, 34, 0 # encoding: [0xf0,0x82,0x17,0x52]
+# CHECK-LE: dmxxinstfdmr512 1, 2, 34, 0 # encoding: [0x52,0x17,0x82,0xf0]
+ dmxxinstfdmr512 1, 2, 34, 0
+
+# CHECK-BE: dmxxinstfdmr512 1, 2, 34, 1 # encoding: [0xf0,0x83,0x17,0x52]
+# CHECK-LE: dmxxinstfdmr512 1, 2, 34, 1 # encoding: [0x52,0x17,0x83,0xf0]
+ dmxxinstfdmr512 1, 2, 34, 1
+
+# CHECK-BE: dmxxinstfdmr256 3, 8, 0 # encoding: [0xf1,0x80,0x47,0x94]
+# CHECK-LE: dmxxinstfdmr256 3, 8, 0 # encoding: [0x94,0x47,0x80,0xf1]
+ dmxxinstfdmr256 3, 8, 0
+
+# CHECK-BE: dmxxinstfdmr256 3, 8, 3 # encoding: [0xf1,0x81,0x4f,0x94]
+# CHECK-LE: dmxxinstfdmr256 3, 8, 3 # encoding: [0x94,0x4f,0x81,0xf1]
+ dmxxinstfdmr256 3, 8, 3
+
+# CHECK-BE: dmsetdmrz 3 # encoding: [0x7d,0x82,0x01,0x62]
+# CHECK-LE: dmsetdmrz 3 # encoding: [0x62,0x01,0x82,0x7d]
+ dmsetdmrz 3
+
+# CHECK-BE: dmmr 4, 5 # encoding: [0x7e,0x06,0xa1,0x62]
+# CHECK-LE: dmmr 4, 5 # encoding: [0x62,0xa1,0x06,0x7e]
+ dmmr 4, 5
+
+# CHECK-BE: dmxor 6, 7 # encoding: [0x7f,0x07,0xe1,0x62]
+# CHECK-LE: dmxor 6, 7 # encoding: [0x62,0xe1,0x07,0x7f]
+ dmxor 6, 7
diff --git a/llvm/utils/TableGen/CodeGenTarget.cpp b/llvm/utils/TableGen/CodeGenTarget.cpp
index 8384a8ceab625..fba168f6e6981 100644
--- a/llvm/utils/TableGen/CodeGenTarget.cpp
+++ b/llvm/utils/TableGen/CodeGenTarget.cpp
@@ -91,6 +91,7 @@ StringRef llvm::getEnumName(MVT::SimpleValueType T) {
case MVT::v256i1: return "MVT::v256i1";
case MVT::v512i1: return "MVT::v512i1";
case MVT::v1024i1: return "MVT::v1024i1";
+ case MVT::v2048i1: return "MVT::v2048i1";
case MVT::v128i2: return "MVT::v128i2";
case MVT::v256i2: return "MVT::v256i2";
case MVT::v64i4: return "MVT::v64i4";
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