[PATCH] D136736: [LSR][TTI][RISCV] Add isAllowDropLSRSolution into TTI and enable it for RISC-V

[Florian Hahn via Phabricator via llvm-commits]

fhahn added a subscriber: dmgreen.
fhahn added a comment.

In D136736#3904001 <https://reviews.llvm.org/D136736#3904001>, @eopXD wrote:

> @fhahn Thank you for checking this in the Arm backend.

I just checked some random failing tests. Another interesting one is `llvm/test/CodeGen/X86/2007-03-15-GEP-Idx-Sink.ll` which also seems to regress. My main point is that I think we should try to avoid fragmentation between backends for generic features such as this one. Having this enabled by default and ironing out the remaining test issues will be much more beneficial for the overall LLVM project. By making sure is is enabled on heavily used architectures like X86 and AArch64 we also ensure that it gets as much testing as possible.

IMO it may be fine to gradually enable it, but I think we first need to understand what the issues with the other tests are. My concern is that after only enabling it for RISCV it will remain enabled for RISCV only

> The regressed result [3] of  CodeGen/Thumb2/LowOverheadLoops/tail-pred-intrinsic-round.ll shows that the {vector contiguous load/store + post-increment instruction} vldrw.u32 and vstrw.32 was not leveraged efficiently, which is why there are two more add.w instructions for the pointers.

I am not too familiar with Thumb2, @dmgreen any thoughts on this?


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https://reviews.llvm.org/D136736