[PATCH] D137233: [LoongArch] Add support for the BranchRelaxation pass

[Xiaodong Liu via Phabricator via llvm-commits]

XiaodongLoong added inline comments.


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Comment at: llvm/lib/Target/LoongArch/LoongArchInstrInfo.cpp:267
+  case LoongArch::PseudoBR:
+    return isInt<28>(BrOffset);
+  }
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arsenm wrote:
> MC can handle relaxing these different immediate offset types; you probably only want to handle the > 28 bit case here (and even then there may be a better way to deal with it which I don't know about it, if you have dedicated registers for it)
> MC can handle relaxing these different immediate offset types; you probably only want to handle the > 28 bit case here (and even then there may be a better way to deal with it which I don't know about it, if you have dedicated registers for it)

The BranchRelaxation pass could handle both condition branch and uncondition branch after I read the code. And I also read the patch from RISCV https://reviews.llvm.org/D40830. I think it might be OK to handle branch relaxing here on LoongArch. As far as I can see, there is no dedicated registers on LoongArch.
Thanks!


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Comment at: llvm/lib/Target/LoongArch/LoongArchInstrInfo.cpp:379
+  // TODO: When there is no scavenged register, it needs to specify a register.
+  assert(Scav != LoongArch::NoRegister && "No register is scavenged!");
+  MRI.replaceRegWith(ScratchReg, Scav);
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SixWeining wrote:
> How about when `assert = off`? Will generate wrong code if `Scav == LoongArch::NoRegister`?
> How about when `assert = off`? Will generate wrong code if `Scav == LoongArch::NoRegister`?

I will handle the condition in other patch. Thanks!


Repository:
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  https://reviews.llvm.org/D137233/new/

https://reviews.llvm.org/D137233