[PATCH] D137066: [AMDGPU] Add amdgcn_s_buffer_load_imm intrinsic

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added a comment.

In D137066#3902128 <https://reviews.llvm.org/D137066#3902128>, @piotr wrote:

> In D137066#3902068 <https://reviews.llvm.org/D137066#3902068>, @nhaehnle wrote:
>
>> I think the question is really: what IR examples are there that could use scalar loads with immediate offsets but don't because instruction selection fails to extract the constant; and why does extracting the constant fail?
>
> All cases of isel not being able to extract the constant I looked at were due to the nodes being scattered over different basic blocks.

This is the kind of case that CodeGenPrepare works around for addressing mode matching. I'd rather add that sort of optimization rather than changing the IR by adding new intrinsics to workaround this


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