[PATCH] D136366: [PowerPC] Add new DMR register classes to Future CPU.

[Stefan Pintilie via Phabricator via llvm-commits]

stefanp updated this revision to Diff 472744.
stefanp added a comment.

Rebased patch to top of main branch.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D136366/new/

https://reviews.llvm.org/D136366

Files:
  llvm/include/llvm/CodeGen/ValueTypes.td
  llvm/include/llvm/IR/Intrinsics.td
  llvm/include/llvm/Support/MachineValueType.h
  llvm/lib/CodeGen/ValueTypes.cpp
  llvm/lib/Target/PowerPC/AsmParser/PPCAsmParser.cpp
  llvm/lib/Target/PowerPC/Disassembler/PPCDisassembler.cpp
  llvm/lib/Target/PowerPC/MCTargetDesc/PPCMCTargetDesc.h
  llvm/lib/Target/PowerPC/PPCInstrFuture.td
  llvm/lib/Target/PowerPC/PPCInstrFutureMMA.td
  llvm/lib/Target/PowerPC/PPCInstrInfo.td
  llvm/lib/Target/PowerPC/PPCRegisterInfo.h
  llvm/lib/Target/PowerPC/PPCRegisterInfo.td
  llvm/lib/Target/PowerPC/PPCRegisterInfoDMR.td
  llvm/lib/Target/PowerPC/PPCScheduleP9.td
  llvm/test/CodeGen/PowerPC/future-check-features.ll
  llvm/test/MC/Disassembler/PowerPC/ppc-encoding-ISAFuture.txt
  llvm/test/MC/Disassembler/PowerPC/ppc64le-encoding-ISAFuture.txt
  llvm/test/MC/PowerPC/ppc-encoding-ISAFuture.s
  llvm/utils/TableGen/CodeGenTarget.cpp

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