[PATCH] D136447: [ARM] Fix vector ule zero lowering

[Dave Green via Phabricator via llvm-commits]

dmgreen added inline comments.


================
Comment at: llvm/lib/Target/ARM/ARMISelLowering.cpp:15209-15218
   // vcmp X, 0, cc -> vcmpz X, cc
   if (isZeroVector(Op1))
     return DAG.getNode(ARMISD::VCMPZ, dl, VT, Op0, N->getOperand(2));
 
   unsigned SwappedCond = getSwappedCondition(Cond);
   if (isValidMVECond(SwappedCond, VT.isFloatingPoint())) {
     // vcmp 0, X, cc -> vcmpz X, reversed(cc)
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aaronpuchert wrote:
> dmgreen wrote:
> > aaronpuchert wrote:
> > > Does something need to be done here?
> > Hmm. Don't think so. What kind of thing do you mean?
> It seems to me that we're also creating `ARMISD::VCMPZ` nodes here, and it doesn't seem obvious to me that we're excluding the problematic `ARMCC::CondCodes`. But I'm probably missing something, just wanted to make sure you're aware of this function.
I see, yeah. This code is only for MVE, and we check isValidMVECond. I think it's OK, and we should have the test coverage for it.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D136447/new/

https://reviews.llvm.org/D136447