[PATCH] D137245: [AArch64][SVE2] Add the SVE2.1 quadword variants of ld1w/ld1d/st1w/st1d

[David Sherwood via Phabricator via llvm-commits]

david-arm created this revision.
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This patch adds the assembly/disassembly for the following instructions:

st1w: Contiguous store words from vector (128-bit vector elements)
st1d: Contiguous store doublewords from vector (128-bit vector elements)
ld1w: Contiguous load unsigned words to vector (128-bit vector elements)
ld1d: Contiguous load unsigned doublewords to vector (128-bit vector elements)

The reference can be found here:
https://developer.arm.com/documentation/ddi0602/2022-09


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D137245

Files:
  llvm/lib/Target/AArch64/AArch64.td
  llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
  llvm/lib/Target/AArch64/AArch64SchedNeoverseN2.td
  llvm/lib/Target/AArch64/SVEInstrFormats.td
  llvm/test/MC/AArch64/SVE2p1/ld1d_q-diagnostics.s
  llvm/test/MC/AArch64/SVE2p1/ld1d_q.s
  llvm/test/MC/AArch64/SVE2p1/ld1w_q-diagnostics.s
  llvm/test/MC/AArch64/SVE2p1/ld1w_q.s
  llvm/test/MC/AArch64/SVE2p1/st1d_q-diagnostics.s
  llvm/test/MC/AArch64/SVE2p1/st1d_q.s
  llvm/test/MC/AArch64/SVE2p1/st1w_q-diagnostics.s
  llvm/test/MC/AArch64/SVE2p1/st1w_q.s

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