[PATCH] D124196: [AMDGPU][SILowerSGPRSpills] Spill SGPRs to virtual VGPRs
Christudasan Devadasan via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Nov 2 04:05:39 PDT 2022
cdevadas added inline comments.
================
Comment at: llvm/lib/Target/AMDGPU/SIFrameLowering.cpp:1351
RS->enterBasicBlock(MBB);
TRI->eliminateFrameIndex(MI, 0, FIOp, RS);
SpillFIs.set(FI);
----------------
Pierre-vh wrote:
> I think this is missing and it's what's causing verification errors with "Using an undefined physical register" that I was talking about.
> The current code just tells the scavenger to enter that block but it doesn't update it to the right instruction, so eliminateFrameIndex is working with information from the start of the BB, not from the MI it's dealing with
An entirely different problem and needs to be implemented separately. The code that handles the register liveness update is implemented in `PEI::replaceFrameIndices` and it tracks the loops and invokes RS->forward() appropriately to update the liveness info. I guess we should bring this code into VGPR to AGPR spill path.
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https://reviews.llvm.org/D124196/new/
https://reviews.llvm.org/D124196
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