[PATCH] D137238: [AMDGPU][MC][GFX11][NFC] Correct VINTERP src operands

[Dmitry Preobrazhensky via Phabricator via llvm-commits]

dp created this revision.
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VINTERP src operands must be VGPRs, but assembler accepts SGPRs as well.


https://reviews.llvm.org/D137238

Files:
  llvm/lib/Target/AMDGPU/VINTERPInstructions.td
  llvm/test/MC/AMDGPU/gfx11_asm_vinterp_errs.s


Index: llvm/test/MC/AMDGPU/gfx11_asm_vinterp_errs.s
===================================================================
--- /dev/null
+++ llvm/test/MC/AMDGPU/gfx11_asm_vinterp_errs.s
@@ -0,0 +1,42 @@
+// RUN: not llvm-mc -arch=amdgcn -mcpu=gfx1100 %s 2>&1 | FileCheck %s -check-prefix=GFX11-ERR --implicit-check-not=error: --strict-whitespace
+
+//===----------------------------------------------------------------------===//
+// VINTERP src operands must be VGPRs.
+// Check that other operand kinds are rejected by assembler.
+//===----------------------------------------------------------------------===//
+
+v_interp_p10_f32 v0, s1, v2, v3
+// GFX11-ERR: error: invalid operand for instruction
+
+v_interp_p10_f32 v0, v1, s2, v3
+// GFX11-ERR: error: invalid operand for instruction
+
+v_interp_p10_f32 v0, v1, v2, s3
+// GFX11-ERR: error: invalid operand for instruction
+
+v_interp_p2_f32 v0, 1, v2, v3
+// GFX11-ERR: error: invalid operand for instruction
+
+v_interp_p2_f32 v0, v1, 2, v3
+// GFX11-ERR: error: invalid operand for instruction
+
+v_interp_p2_f32 v0, v1, v2, 3
+// GFX11-ERR: error: invalid operand for instruction
+
+v_interp_p10_f16_f32 v0, s1, v2, v3
+// GFX11-ERR: error: invalid operand for instruction
+
+v_interp_p10_f16_f32 v0, v1, s2, v3
+// GFX11-ERR: error: invalid operand for instruction
+
+v_interp_p10_f16_f32 v0, v1, v2, s3
+// GFX11-ERR: error: invalid operand for instruction
+
+v_interp_p2_f16_f32 v0, 1, v2, v3
+// GFX11-ERR: error: invalid operand for instruction
+
+v_interp_p2_f16_f32 v0, v1, 2, v3
+// GFX11-ERR: error: invalid operand for instruction
+
+v_interp_p2_f16_f32 v0, v1, v2, 3
+// GFX11-ERR: error: invalid operand for instruction
Index: llvm/lib/Target/AMDGPU/VINTERPInstructions.td
===================================================================
--- llvm/lib/Target/AMDGPU/VINTERPInstructions.td
+++ llvm/lib/Target/AMDGPU/VINTERPInstructions.td
@@ -63,10 +63,14 @@
   let HasOpSel = 0;
   let HasModifiers = 1;
 
+  let Src0Mod = FPVRegInputMods;
+  let Src1Mod = FPVRegInputMods;
+  let Src2Mod = FPVRegInputMods;
+
   let Outs64 = (outs VGPR_32:$vdst);
-  let Ins64 = (ins Src0Mod:$src0_modifiers, VRegSrc_32:$src0,
-                   Src1Mod:$src1_modifiers, VRegSrc_32:$src1,
-                   Src2Mod:$src2_modifiers, VRegSrc_32:$src2,
+  let Ins64 = (ins Src0Mod:$src0_modifiers, VGPR_32:$src0,
+                   Src1Mod:$src1_modifiers, VGPR_32:$src1,
+                   Src2Mod:$src2_modifiers, VGPR_32:$src2,
                    clampmod:$clamp,
                    wait_exp:$waitexp);
 
@@ -77,10 +81,14 @@
   let HasOpSel = 1;
   let HasModifiers = 1;
 
+  let Src0Mod = FPVRegInputMods;
+  let Src1Mod = FPVRegInputMods;
+  let Src2Mod = FPVRegInputMods;
+
   let Outs64 = (outs VGPR_32:$vdst);
-  let Ins64 = (ins Src0Mod:$src0_modifiers, VRegSrc_32:$src0,
-                   Src1Mod:$src1_modifiers, VRegSrc_32:$src1,
-                   Src2Mod:$src2_modifiers, VRegSrc_32:$src2,
+  let Ins64 = (ins Src0Mod:$src0_modifiers, VGPR_32:$src0,
+                   Src1Mod:$src1_modifiers, VGPR_32:$src1,
+                   Src2Mod:$src2_modifiers, VGPR_32:$src2,
                    clampmod:$clamp, op_sel0:$op_sel,
                    wait_exp:$waitexp);
 


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