[llvm] 9a9b904 - [AArch64][SVE2] Add the SVE2.1 ld1q gather & st1q scatter instructions
David Sherwood via llvm-commits
llvm-commits at lists.llvm.org
Wed Nov 2 01:58:25 PDT 2022
Author: David Sherwood
Date: 2022-11-02T08:58:19Z
New Revision: 9a9b904b871af2ee0b846c31fa1c2570528ce4a4
URL: https://github.com/llvm/llvm-project/commit/9a9b904b871af2ee0b846c31fa1c2570528ce4a4
DIFF: https://github.com/llvm/llvm-project/commit/9a9b904b871af2ee0b846c31fa1c2570528ce4a4.diff
LOG: [AArch64][SVE2] Add the SVE2.1 ld1q gather & st1q scatter instructions
This patch adds the assembly/disassembly for the following instructions:
ld1q : Gather load quadwords
st1q : Scatter store quadwords
The reference can be found here:
https://developer.arm.com/documentation/ddi0602/2022-09
Differential Revision: https://reviews.llvm.org/D137167
Added:
llvm/test/MC/AArch64/SVE2p1/ld1q-diagnostics.s
llvm/test/MC/AArch64/SVE2p1/ld1q.s
llvm/test/MC/AArch64/SVE2p1/st1q-diagnostics.s
llvm/test/MC/AArch64/SVE2p1/st1q.s
Modified:
llvm/lib/Target/AArch64/AArch64RegisterInfo.td
llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
llvm/lib/Target/AArch64/SVEInstrFormats.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/AArch64/AArch64RegisterInfo.td b/llvm/lib/Target/AArch64/AArch64RegisterInfo.td
index bc3b88c61e8a6..8a41cd5c4d49b 100644
--- a/llvm/lib/Target/AArch64/AArch64RegisterInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64RegisterInfo.td
@@ -1147,6 +1147,10 @@ def Z_d : RegisterOperand<ZPR, "printTypedVectorList<0,'d'>"> {
let ParserMatchClass = ZPRVectorList<64, 1>;
}
+def Z_q : RegisterOperand<ZPR, "printTypedVectorList<0,'q'>"> {
+ let ParserMatchClass = ZPRVectorList<128, 1>;
+}
+
def ZZ_b : RegisterOperand<ZPR2, "printTypedVectorList<0,'b'>"> {
let ParserMatchClass = ZPRVectorList<8, 2>;
}
diff --git a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
index 4099884040c1a..1549295a72bc4 100644
--- a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
@@ -1108,6 +1108,9 @@ let Predicates = [HasSVE] in {
defm GLDFF1W_D : sve_mem_64b_gld_vs2_64_unscaled<0b1011, "ldff1w", AArch64ldff1_gather_z, nxv2i32>;
defm GLD1D : sve_mem_64b_gld_vs2_64_unscaled<0b1110, "ld1d", AArch64ld1_gather_z, nxv2i64>;
defm GLDFF1D : sve_mem_64b_gld_vs2_64_unscaled<0b1111, "ldff1d", AArch64ldff1_gather_z, nxv2i64>;
+ let Predicates = [HasSVE2p1] in {
+ defm GLD1Q : sve_mem_128b_gld_64_unscaled<"ld1q">;
+ }
// Gathers using scaled 64-bit offsets, e.g.
// ld1h z0.d, p0/z, [x0, z0.d, lsl #1]
@@ -1321,6 +1324,9 @@ let Predicates = [HasSVE] in {
defm SST1H_D : sve_mem_sst_sv_64_unscaled<0b01, "st1h", AArch64st1_scatter, nxv2i16>;
defm SST1W_D : sve_mem_sst_sv_64_unscaled<0b10, "st1w", AArch64st1_scatter, nxv2i32>;
defm SST1D : sve_mem_sst_sv_64_unscaled<0b11, "st1d", AArch64st1_scatter, nxv2i64>;
+ let Predicates = [HasSVE2p1] in {
+ defm SST1Q : sve_mem_sst_128b_64_unscaled<"st1q">;
+ }
// Scatters using scaled 64-bit offsets, e.g.
// st1h z0.d, p0, [x0, z0.d, lsl #1]
diff --git a/llvm/lib/Target/AArch64/SVEInstrFormats.td b/llvm/lib/Target/AArch64/SVEInstrFormats.td
index 63098194e45c5..01ef367fef752 100644
--- a/llvm/lib/Target/AArch64/SVEInstrFormats.td
+++ b/llvm/lib/Target/AArch64/SVEInstrFormats.td
@@ -9146,3 +9146,56 @@ multiclass sve2p1_int_while_rr_pair<string mnemonic, bits<3> opc> {
def _S : sve2p1_int_while_rr_pair<mnemonic, 0b10, opc, PP_s_mul_r>;
def _D : sve2p1_int_while_rr_pair<mnemonic, 0b11, opc, PP_d_mul_r>;
}
+
+
+class sve_mem_128b_gld_64_unscaled<string mnemonic>
+ : I<(outs Z_q:$Zt), (ins PPR3bAny:$Pg, ZPR64:$Zn, GPR64:$Rm),
+ mnemonic, "\t$Zt, $Pg/z, [$Zn, $Rm]",
+ "", []>, Sched<[]> {
+ bits<5> Zt;
+ bits<5> Zn;
+ bits<3> Pg;
+ bits<5> Rm;
+ let Inst{31-21} = 0b11000100000;
+ let Inst{20-16} = Rm;
+ let Inst{15-13} = 0b101;
+ let Inst{12-10} = Pg;
+ let Inst{9-5} = Zn;
+ let Inst{4-0} = Zt;
+
+ let mayLoad = 1;
+}
+
+
+multiclass sve_mem_128b_gld_64_unscaled<string mnemonic> {
+ def NAME : sve_mem_128b_gld_64_unscaled<mnemonic>;
+
+ def : InstAlias<mnemonic # " $Zt, $Pg/z, [$Zn]",
+ (!cast<Instruction>(NAME) Z_q:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, XZR), 1>;
+}
+
+class sve_mem_sst_128b_64_unscaled<string mnemonic>
+ : I<(outs ), (ins Z_q:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, GPR64:$Rm),
+ mnemonic, "\t$Zt, $Pg, [$Zn, $Rm]",
+ "", []>, Sched<[]> {
+ bits<5> Zt;
+ bits<5> Zn;
+ bits<3> Pg;
+ bits<5> Rm;
+ let Inst{31-21} = 0b11100100001;
+ let Inst{20-16} = Rm;
+ let Inst{15-13} = 0b001;
+ let Inst{12-10} = Pg;
+ let Inst{9-5} = Zn;
+ let Inst{4-0} = Zt;
+
+ let mayStore = 1;
+}
+
+
+multiclass sve_mem_sst_128b_64_unscaled<string mnemonic> {
+ def NAME : sve_mem_sst_128b_64_unscaled<mnemonic>;
+
+ def : InstAlias<mnemonic # " $Zt, $Pg, [$Zn]",
+ (!cast<Instruction>(NAME) Z_q:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, XZR), 1>;
+}
diff --git a/llvm/test/MC/AArch64/SVE2p1/ld1q-diagnostics.s b/llvm/test/MC/AArch64/SVE2p1/ld1q-diagnostics.s
new file mode 100644
index 0000000000000..c9ec51360e885
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE2p1/ld1q-diagnostics.s
@@ -0,0 +1,43 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 2>&1 < %s | FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Invalid predicate register
+
+ld1q {z0.q}, p8/z, [z0.d, x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// CHECK-NEXT: ld1q {z0.q}, p8/z, [z0.d, x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1q {z23.q}, p2/m, [z3.d]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: ld1q {z23.q}, p2/m, [z3.d]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+ld1q {z21.q}, p2.q, [z5.d]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// CHECK-NEXT: ld1q {z21.q}, p2.q, [z5.d]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid order of base & offset
+
+ld1q {z0.q}, p0/z, [x0, z0.d]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: ld1q {z0.q}, p0/z, [x0, z0.d]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid general purpose register
+
+ld1q {z0.q}, p0/z, [z0.d, sp]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: ld1q {z0.q}, p0/z, [z0.d, sp]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid suffixes
+
+ld1q {z0.q}, p0/z, [z2.s]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: ld1q {z0.q}, p0/z, [z2.s]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE2p1/ld1q.s b/llvm/test/MC/AArch64/SVE2p1/ld1q.s
new file mode 100644
index 0000000000000..dc6e904d0fa0a
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE2p1/ld1q.s
@@ -0,0 +1,38 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p1 < %s \
+// RUN: | llvm-objdump -d --mattr=+sve2p1 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p1 < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 < %s \
+// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN: | llvm-mc -triple=aarch64 -mattr=+sve2p1 -disassemble -show-encoding \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+
+ld1q {z0.q}, p0/z, [z0.d, x0] // 11000100-00000000-10100000-00000000
+// CHECK-INST: ld1q { z0.q }, p0/z, [z0.d, x0]
+// CHECK-ENCODING: [0x00,0xa0,0x00,0xc4]
+// CHECK-ERROR: instruction requires: sve2p1
+// CHECK-UNKNOWN: c400a000 <unknown>
+
+ld1q {z21.q}, p5/z, [z10.d, x21] // 11000100-00010101-10110101-01010101
+// CHECK-INST: ld1q { z21.q }, p5/z, [z10.d, x21]
+// CHECK-ENCODING: [0x55,0xb5,0x15,0xc4]
+// CHECK-ERROR: instruction requires: sve2p1
+// CHECK-UNKNOWN: c415b555 <unknown>
+
+ld1q {z23.q}, p3/z, [z13.d, x8] // 11000100-00001000-10101101-10110111
+// CHECK-INST: ld1q { z23.q }, p3/z, [z13.d, x8]
+// CHECK-ENCODING: [0xb7,0xad,0x08,0xc4]
+// CHECK-ERROR: instruction requires: sve2p1
+// CHECK-UNKNOWN: c408adb7 <unknown>
+
+ld1q {z31.q}, p7/z, [z31.d] // 11000100-00011111-10111111-11111111
+// CHECK-INST: ld1q { z31.q }, p7/z, [z31.d]
+// CHECK-ENCODING: [0xff,0xbf,0x1f,0xc4]
+// CHECK-ERROR: instruction requires: sve2p1
+// CHECK-UNKNOWN: c41fbfff <unknown>
+
diff --git a/llvm/test/MC/AArch64/SVE2p1/st1q-diagnostics.s b/llvm/test/MC/AArch64/SVE2p1/st1q-diagnostics.s
new file mode 100644
index 0000000000000..fc45a528b8d48
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE2p1/st1q-diagnostics.s
@@ -0,0 +1,43 @@
+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 2>&1 < %s | FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Invalid predicate register
+
+st1q {z0.q}, p8, [z0.d, x0]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// CHECK-NEXT: st1q {z0.q}, p8, [z0.d, x0]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st1q {z23.q}, p2/m, [z3.d]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: st1q {z23.q}, p2/m, [z3.d]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+st1q {z21.q}, p2.q, [z5.d]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
+// CHECK-NEXT: st1q {z21.q}, p2.q, [z5.d]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid order of base & offset
+
+st1q {z0.q}, p0, [x0, z0.d]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: st1q {z0.q}, p0, [x0, z0.d]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid general purpose register
+
+st1q {z0.q}, p0, [z0.d, sp]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: st1q {z0.q}, p0, [z0.d, sp]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid suffixes
+
+st1q {z0.q}, p0, [z2.s]
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
+// CHECK-NEXT: st1q {z0.q}, p0, [z2.s]
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
diff --git a/llvm/test/MC/AArch64/SVE2p1/st1q.s b/llvm/test/MC/AArch64/SVE2p1/st1q.s
new file mode 100644
index 0000000000000..313e7d7e0f17e
--- /dev/null
+++ b/llvm/test/MC/AArch64/SVE2p1/st1q.s
@@ -0,0 +1,38 @@
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 < %s \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p1 < %s \
+// RUN: | llvm-objdump -d --mattr=+sve2p1 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve2p1 < %s \
+// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 < %s \
+// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN: | llvm-mc -triple=aarch64 -mattr=+sve2p1 -disassemble -show-encoding \
+// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+
+st1q {z0.q}, p0, [z0.d, x0] // 11100100-00100000-00100000-00000000
+// CHECK-INST: st1q { z0.q }, p0, [z0.d, x0]
+// CHECK-ENCODING: [0x00,0x20,0x20,0xe4]
+// CHECK-ERROR: instruction requires: sve2p1
+// CHECK-UNKNOWN: e4202000 <unknown>
+
+st1q {z21.q}, p5, [z10.d, x21] // 11100100-00110101-00110101-01010101
+// CHECK-INST: st1q { z21.q }, p5, [z10.d, x21]
+// CHECK-ENCODING: [0x55,0x35,0x35,0xe4]
+// CHECK-ERROR: instruction requires: sve2p1
+// CHECK-UNKNOWN: e4353555 <unknown>
+
+st1q {z23.q}, p3, [z13.d, x8] // 11100100-00101000-00101101-10110111
+// CHECK-INST: st1q { z23.q }, p3, [z13.d, x8]
+// CHECK-ENCODING: [0xb7,0x2d,0x28,0xe4]
+// CHECK-ERROR: instruction requires: sve2p1
+// CHECK-UNKNOWN: e4282db7 <unknown>
+
+st1q {z31.q}, p7, [z31.d] // 11100100-00111111-00111111-11111111
+// CHECK-INST: st1q { z31.q }, p7, [z31.d]
+// CHECK-ENCODING: [0xff,0x3f,0x3f,0xe4]
+// CHECK-ERROR: instruction requires: sve2p1
+// CHECK-UNKNOWN: e43f3fff <unknown>
+
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