[PATCH] D135102: [AArch64] Compare BFI and ORR with left-shifted operand for OR instruction selection.

[Mingming Liu via Phabricator via llvm-commits]

mingmingl updated this revision to Diff 472519.
mingmingl edited the summary of this revision.
mingmingl added a comment.

fix a bug around width computation (updated commit message and patch summary as well), and adjust whitespace in a few test cases (mainly those not updated by `utils/update_llc_test_checks.py`) to remove irrelevant diff.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D135102/new/

https://reviews.llvm.org/D135102

Files:
  llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
  llvm/test/CodeGen/AArch64/arm64-bitfield-extract.ll
  llvm/test/CodeGen/AArch64/arm64-non-pow2-ldst.ll
  llvm/test/CodeGen/AArch64/arm64-strict-align.ll
  llvm/test/CodeGen/AArch64/arm64_32.ll
  llvm/test/CodeGen/AArch64/bfis-in-loop.ll
  llvm/test/CodeGen/AArch64/bitfield-insert.ll
  llvm/test/CodeGen/AArch64/build-pair-isel.ll
  llvm/test/CodeGen/AArch64/funnel-shift-rot.ll
  llvm/test/CodeGen/AArch64/load-combine-big-endian.ll
  llvm/test/CodeGen/AArch64/load-combine.ll
  llvm/test/CodeGen/AArch64/logic-shift.ll
  llvm/test/CodeGen/AArch64/nontemporal-load.ll
  llvm/test/CodeGen/AArch64/rotate-extract.ll
  llvm/test/CodeGen/AArch64/trunc-to-tbl.ll
  llvm/test/CodeGen/AArch64/urem-seteq.ll
  llvm/test/CodeGen/AArch64/vec_uaddo.ll
  llvm/test/CodeGen/AArch64/vec_umulo.ll

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