[PATCH] D124192: [AMDGPU] Callee must always spill writelane VGPRs

[Matt Arsenault via Phabricator via llvm-commits]

arsenm accepted this revision.
arsenm added inline comments.


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Comment at: llvm/lib/Target/AMDGPU/SIFrameLowering.cpp:1267-1272
+      // TODO: Handle this elsewhere at an early point. Walking through all MBBs
+      // here would be a bad heuristic. A better way should be by calling
+      // allocateWWMSpill during the regalloc pipeline whenever a physical
+      // register is allocated for the intended virtual registers. That will
+      // also help excluding the general use of WRITELANE/READLANE intrinsics
+      // that won't really need any such special handling.
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Can you open an issue for this?


Repository:
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CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D124192/new/

https://reviews.llvm.org/D124192