[PATCH] D136014: [AArch64] Improve codegen for shifted mask op

[Dave Green via Phabricator via llvm-commits]

dmgreen accepted this revision.
dmgreen added a comment.
This revision is now accepted and ready to land.

Thanks. This LGTM



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Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:14404
+  // The special case is ((x >> C) & mask) << C.
+  // It can be combine to x & (mask << C) by return true
   if (ShiftLHS.getOpcode() == ISD::AND && (VT == MVT::i32 || VT == MVT::i64) &&
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This comment doesn't parse very well. Perhaps try to reword the sentance.


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  https://reviews.llvm.org/D136014/new/

https://reviews.llvm.org/D136014