[llvm] 2e999b7 - Allow scalable vectors in ComputeNumSignBits and isKnownNonNull
Philip Reames via llvm-commits
llvm-commits at lists.llvm.org
Tue Nov 1 09:29:49 PDT 2022
Author: Philip Reames
Date: 2022-11-01T09:29:42-07:00
New Revision: 2e999b7dd1934a44d38c3a753460f1e5a217e9a5
URL: https://github.com/llvm/llvm-project/commit/2e999b7dd1934a44d38c3a753460f1e5a217e9a5
DIFF: https://github.com/llvm/llvm-project/commit/2e999b7dd1934a44d38c3a753460f1e5a217e9a5.diff
LOG: Allow scalable vectors in ComputeNumSignBits and isKnownNonNull
This is a follow up to D136470 which extends the same scheme used there to ComputeNumSignBits and isKnownNonNull. As a reminder, for scalable vectors we track a single bit which is implicitly broadcast to all lanes. We do not know how many lanes there are statically, and thus have to be conservative along paths which require exact sizes.
Differential Revision: https://reviews.llvm.org/D137046
Added:
Modified:
llvm/lib/Analysis/ValueTracking.cpp
llvm/test/Transforms/InstCombine/logical-select.ll
llvm/test/Transforms/InstCombine/select.ll
Removed:
################################################################################
diff --git a/llvm/lib/Analysis/ValueTracking.cpp b/llvm/lib/Analysis/ValueTracking.cpp
index 0606ce7fd6f1..be009501f2e9 100644
--- a/llvm/lib/Analysis/ValueTracking.cpp
+++ b/llvm/lib/Analysis/ValueTracking.cpp
@@ -375,11 +375,6 @@ static unsigned ComputeNumSignBits(const Value *V, const APInt &DemandedElts,
static unsigned ComputeNumSignBits(const Value *V, unsigned Depth,
const Query &Q) {
- // FIXME: We currently have no way to represent the DemandedElts of a scalable
- // vector
- if (isa<ScalableVectorType>(V->getType()))
- return 1;
-
auto *FVTy = dyn_cast<FixedVectorType>(V->getType());
APInt DemandedElts =
FVTy ? APInt::getAllOnes(FVTy->getNumElements()) : APInt(1, 1);
@@ -2449,10 +2444,6 @@ static bool isNonZeroRecurrence(const PHINode *PN) {
/// Supports values with integer or pointer type and vectors of integers.
bool isKnownNonZero(const Value *V, const APInt &DemandedElts, unsigned Depth,
const Query &Q) {
- // FIXME: We currently have no way to represent the DemandedElts of a scalable
- // vector
- if (isa<ScalableVectorType>(V->getType()))
- return false;
#ifndef NDEBUG
Type *Ty = V->getType();
@@ -2574,14 +2565,18 @@ bool isKnownNonZero(const Value *V, const APInt &DemandedElts, unsigned Depth,
// Note that we have to take special care to avoid looking through
// truncating casts, e.g., int2ptr/ptr2int with appropriate sizes, as well
// as casts that can alter the value, e.g., AddrSpaceCasts.
- if (Q.DL.getTypeSizeInBits(I->getOperand(0)->getType()).getFixedSize() <=
+ if (!isa<ScalableVectorType>(I->getOperand(0)->getType()) &&
+ !isa<ScalableVectorType>(I->getType()) &&
+ Q.DL.getTypeSizeInBits(I->getOperand(0)->getType()).getFixedSize() <=
Q.DL.getTypeSizeInBits(I->getType()).getFixedSize())
return isKnownNonZero(I->getOperand(0), Depth, Q);
break;
case Instruction::PtrToInt:
// Similar to int2ptr above, we can look through ptr2int here if the cast
// is a no-op or an extend and not a truncate.
- if (Q.DL.getTypeSizeInBits(I->getOperand(0)->getType()).getFixedSize() <=
+ if (!isa<ScalableVectorType>(I->getOperand(0)->getType()) &&
+ !isa<ScalableVectorType>(I->getType()) &&
+ Q.DL.getTypeSizeInBits(I->getOperand(0)->getType()).getFixedSize() <=
Q.DL.getTypeSizeInBits(I->getType()).getFixedSize())
return isKnownNonZero(I->getOperand(0), Depth, Q);
break;
@@ -2740,11 +2735,6 @@ bool isKnownNonZero(const Value *V, const APInt &DemandedElts, unsigned Depth,
}
bool isKnownNonZero(const Value* V, unsigned Depth, const Query& Q) {
- // FIXME: We currently have no way to represent the DemandedElts of a scalable
- // vector
- if (isa<ScalableVectorType>(V->getType()))
- return false;
-
auto *FVTy = dyn_cast<FixedVectorType>(V->getType());
APInt DemandedElts =
FVTy ? APInt::getAllOnes(FVTy->getNumElements()) : APInt(1, 1);
@@ -3096,12 +3086,6 @@ static unsigned ComputeNumSignBitsImpl(const Value *V,
const APInt &DemandedElts,
unsigned Depth, const Query &Q) {
Type *Ty = V->getType();
-
- // FIXME: We currently have no way to represent the DemandedElts of a scalable
- // vector
- if (isa<ScalableVectorType>(Ty))
- return 1;
-
#ifndef NDEBUG
assert(Depth <= MaxAnalysisRecursionDepth && "Limit Search Depth");
diff --git a/llvm/test/Transforms/InstCombine/logical-select.ll b/llvm/test/Transforms/InstCombine/logical-select.ll
index 8fe517ad4145..4a11335964ba 100644
--- a/llvm/test/Transforms/InstCombine/logical-select.ll
+++ b/llvm/test/Transforms/InstCombine/logical-select.ll
@@ -742,13 +742,11 @@ define <2 x i64> @bitcast_vec_cond(<16 x i1> %cond, <2 x i64> %c, <2 x i64> %d)
define <vscale x 2 x i64> @bitcast_vec_cond_scalable(<vscale x 16 x i1> %cond, <vscale x 2 x i64> %c, <vscale x 2 x i64> %d) {
; CHECK-LABEL: @bitcast_vec_cond_scalable(
-; CHECK-NEXT: [[S:%.*]] = sext <vscale x 16 x i1> [[COND:%.*]] to <vscale x 16 x i8>
-; CHECK-NEXT: [[T9:%.*]] = bitcast <vscale x 16 x i8> [[S]] to <vscale x 2 x i64>
-; CHECK-NEXT: [[NOTT9:%.*]] = xor <vscale x 2 x i64> [[T9]], shufflevector (<vscale x 2 x i64> insertelement (<vscale x 2 x i64> poison, i64 -1, i32 0), <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer)
-; CHECK-NEXT: [[T11:%.*]] = and <vscale x 2 x i64> [[NOTT9]], [[C:%.*]]
-; CHECK-NEXT: [[T12:%.*]] = and <vscale x 2 x i64> [[T9]], [[D:%.*]]
-; CHECK-NEXT: [[R:%.*]] = or <vscale x 2 x i64> [[T11]], [[T12]]
-; CHECK-NEXT: ret <vscale x 2 x i64> [[R]]
+; CHECK-NEXT: [[TMP1:%.*]] = bitcast <vscale x 2 x i64> [[D:%.*]] to <vscale x 16 x i8>
+; CHECK-NEXT: [[TMP2:%.*]] = bitcast <vscale x 2 x i64> [[C:%.*]] to <vscale x 16 x i8>
+; CHECK-NEXT: [[TMP3:%.*]] = select <vscale x 16 x i1> [[COND:%.*]], <vscale x 16 x i8> [[TMP1]], <vscale x 16 x i8> [[TMP2]]
+; CHECK-NEXT: [[TMP4:%.*]] = bitcast <vscale x 16 x i8> [[TMP3]] to <vscale x 2 x i64>
+; CHECK-NEXT: ret <vscale x 2 x i64> [[TMP4]]
;
%s = sext <vscale x 16 x i1> %cond to <vscale x 16 x i8>
%t9 = bitcast <vscale x 16 x i8> %s to <vscale x 2 x i64>
diff --git a/llvm/test/Transforms/InstCombine/select.ll b/llvm/test/Transforms/InstCombine/select.ll
index cc72e3579c40..e16f01bb520d 100644
--- a/llvm/test/Transforms/InstCombine/select.ll
+++ b/llvm/test/Transforms/InstCombine/select.ll
@@ -3409,11 +3409,10 @@ define <vscale x 2 x i32> @and_constant_select_svec(<vscale x 2 x i32> %x, <vsca
ret <vscale x 2 x i32> %b
}
-; TODO: shl should be nsw
define <vscale x 2 x i32> @scalable_sign_bits(<vscale x 2 x i8> %x) {
; CHECK-LABEL: @scalable_sign_bits(
; CHECK-NEXT: [[A:%.*]] = sext <vscale x 2 x i8> [[X:%.*]] to <vscale x 2 x i32>
-; CHECK-NEXT: [[B:%.*]] = shl <vscale x 2 x i32> [[A]], shufflevector (<vscale x 2 x i32> insertelement (<vscale x 2 x i32> poison, i32 16, i32 0), <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer)
+; CHECK-NEXT: [[B:%.*]] = shl nsw <vscale x 2 x i32> [[A]], shufflevector (<vscale x 2 x i32> insertelement (<vscale x 2 x i32> poison, i32 16, i32 0), <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer)
; CHECK-NEXT: ret <vscale x 2 x i32> [[B]]
;
%a = sext <vscale x 2 x i8> %x to <vscale x 2 x i32>
@@ -3421,12 +3420,10 @@ define <vscale x 2 x i32> @scalable_sign_bits(<vscale x 2 x i8> %x) {
ret <vscale x 2 x i32> %b
}
-; TODO: can use ult
define <vscale x 2 x i1> @scalable_non_zero(<vscale x 2 x i32> %x) {
; CHECK-LABEL: @scalable_non_zero(
; CHECK-NEXT: [[A:%.*]] = or <vscale x 2 x i32> [[X:%.*]], shufflevector (<vscale x 2 x i32> insertelement (<vscale x 2 x i32> poison, i32 1, i32 0), <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer)
-; CHECK-NEXT: [[B:%.*]] = add nsw <vscale x 2 x i32> [[A]], shufflevector (<vscale x 2 x i32> insertelement (<vscale x 2 x i32> poison, i32 -1, i32 0), <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer)
-; CHECK-NEXT: [[CMP:%.*]] = icmp ult <vscale x 2 x i32> [[B]], shufflevector (<vscale x 2 x i32> insertelement (<vscale x 2 x i32> poison, i32 56, i32 0), <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer)
+; CHECK-NEXT: [[CMP:%.*]] = icmp ule <vscale x 2 x i32> [[A]], shufflevector (<vscale x 2 x i32> insertelement (<vscale x 2 x i32> poison, i32 56, i32 0), <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer)
; CHECK-NEXT: ret <vscale x 2 x i1> [[CMP]]
;
%a = or <vscale x 2 x i32> %x, shufflevector (<vscale x 2 x i32> insertelement (<vscale x 2 x i32> poison, i32 1, i32 0), <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer)
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