[llvm] b124295 - Implement support for AArch64ISD::MOVI in computeKnownBits

[Adrian Tong via llvm-commits]

Author: Adrian Tong
Date: 2022-11-01T15:50:08Z
New Revision: b124295ef60f4ea5bc77b38d12da608e10d7d34e

URL: https://github.com/llvm/llvm-project/commit/b124295ef60f4ea5bc77b38d12da608e10d7d34e
DIFF: https://github.com/llvm/llvm-project/commit/b124295ef60f4ea5bc77b38d12da608e10d7d34e.diff

LOG: Implement support for AArch64ISD::MOVI in computeKnownBits

This helps simplify a USHR+ORR into USRA on AArch64

Differential Revision: https://reviews.llvm.org/D137108

Added: 
    

Modified: 
    llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    llvm/test/CodeGen/AArch64/fast-isel-cmp-vec.ll
    llvm/test/CodeGen/AArch64/shift-accumulate.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index cc0d92fd25f8..6571ddd7cb12 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -1972,6 +1972,12 @@ void AArch64TargetLowering::computeKnownBitsForTargetNode(
     Known = KnownBits::ashr(Known, Known2);
     break;
   }
+  case AArch64ISD::MOVI: {
+    ConstantSDNode *CN = cast<ConstantSDNode>(Op->getOperand(0));
+    Known =
+        KnownBits::makeConstant(APInt(Known.getBitWidth(), CN->getZExtValue()));
+    break;
+  }
   case AArch64ISD::LOADgot:
   case AArch64ISD::ADDlow: {
     if (!Subtarget->isTargetILP32())
@@ -23114,6 +23120,7 @@ bool AArch64TargetLowering::SimplifyDemandedBitsForTargetNode(
 
 bool AArch64TargetLowering::isTargetCanonicalConstantNode(SDValue Op) const {
   return Op.getOpcode() == AArch64ISD::DUP ||
+         Op.getOpcode() == AArch64ISD::MOVI ||
          (Op.getOpcode() == ISD::EXTRACT_SUBVECTOR &&
           Op.getOperand(0).getOpcode() == AArch64ISD::DUP) ||
          TargetLowering::isTargetCanonicalConstantNode(Op);

diff  --git a/llvm/test/CodeGen/AArch64/fast-isel-cmp-vec.ll b/llvm/test/CodeGen/AArch64/fast-isel-cmp-vec.ll
index 644a0ef51261..ee2d940b8573 100644
--- a/llvm/test/CodeGen/AArch64/fast-isel-cmp-vec.ll
+++ b/llvm/test/CodeGen/AArch64/fast-isel-cmp-vec.ll
@@ -86,7 +86,6 @@ define <16 x i8> @icmp_constfold_v16i8(<16 x i8> %a) {
 ; CHECK-LABEL: icmp_constfold_v16i8:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    movi.16b v0, #1
-; CHECK-NEXT:    and.16b v0, v0, v0
 ; CHECK-NEXT:    ret
   %1 = icmp eq <16 x i8> %a, %a
   br label %bb2

diff  --git a/llvm/test/CodeGen/AArch64/shift-accumulate.ll b/llvm/test/CodeGen/AArch64/shift-accumulate.ll
index eb435830094a..bea01fc6c28e 100644
--- a/llvm/test/CodeGen/AArch64/shift-accumulate.ll
+++ b/llvm/test/CodeGen/AArch64/shift-accumulate.ll
@@ -129,8 +129,7 @@ define <8 x i16> @usra_with_movi_v8i16(<16 x i8> %0, <16 x i8> %1) {
 ; CHECK-NEXT:    movi v2.16b, #1
 ; CHECK-NEXT:    cmeq v0.16b, v0.16b, v1.16b
 ; CHECK-NEXT:    and v0.16b, v0.16b, v2.16b
-; CHECK-NEXT:    ushr v1.8h, v0.8h, #7
-; CHECK-NEXT:    orr v0.16b, v1.16b, v0.16b
+; CHECK-NEXT:    usra v0.8h, v0.8h, #7
 ; CHECK-NEXT:    ret
   %3 = icmp eq <16 x i8> %0, %1
   %4 = zext <16 x i1> %3 to <16 x i8>
@@ -148,8 +147,7 @@ define <4 x i32> @usra_with_movi_v4i32(<16 x i8> %0, <16 x i8> %1) {
 ; CHECK-NEXT:    movi v2.16b, #1
 ; CHECK-NEXT:    cmeq v0.16b, v0.16b, v1.16b
 ; CHECK-NEXT:    and v0.16b, v0.16b, v2.16b
-; CHECK-NEXT:    ushr v1.4s, v0.4s, #15
-; CHECK-NEXT:    orr v0.16b, v1.16b, v0.16b
+; CHECK-NEXT:    usra v0.4s, v0.4s, #15
 ; CHECK-NEXT:    ret
   %3 = icmp eq <16 x i8> %0, %1
   %4 = zext <16 x i1> %3 to <16 x i8>
@@ -167,8 +165,7 @@ define <2 x i64> @usra_with_movi_v2i64(<16 x i8> %0, <16 x i8> %1) {
 ; CHECK-NEXT:    movi v2.16b, #1
 ; CHECK-NEXT:    cmeq v0.16b, v0.16b, v1.16b
 ; CHECK-NEXT:    and v0.16b, v0.16b, v2.16b
-; CHECK-NEXT:    ushr v1.2d, v0.2d, #31
-; CHECK-NEXT:    orr v0.16b, v1.16b, v0.16b
+; CHECK-NEXT:    usra v0.2d, v0.2d, #31
 ; CHECK-NEXT:    ret
   %3 = icmp eq <16 x i8> %0, %1
   %4 = zext <16 x i1> %3 to <16 x i8>