[PATCH] D137108: Implement support for AArch64ISD::MOVI in computeKnownBits

[Adrian Tong via Phabricator via llvm-commits]

adriantong1024 updated this revision to Diff 472318.
adriantong1024 added a comment.

Rebase.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D137108/new/

https://reviews.llvm.org/D137108

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/test/CodeGen/AArch64/fast-isel-cmp-vec.ll
  llvm/test/CodeGen/AArch64/shift-accumulate.ll


Index: llvm/test/CodeGen/AArch64/shift-accumulate.ll
===================================================================
--- llvm/test/CodeGen/AArch64/shift-accumulate.ll
+++ llvm/test/CodeGen/AArch64/shift-accumulate.ll
@@ -129,8 +129,7 @@
 ; CHECK-NEXT:    movi v2.16b, #1
 ; CHECK-NEXT:    cmeq v0.16b, v0.16b, v1.16b
 ; CHECK-NEXT:    and v0.16b, v0.16b, v2.16b
-; CHECK-NEXT:    ushr v1.8h, v0.8h, #7
-; CHECK-NEXT:    orr v0.16b, v1.16b, v0.16b
+; CHECK-NEXT:    usra v0.8h, v0.8h, #7
 ; CHECK-NEXT:    ret
   %3 = icmp eq <16 x i8> %0, %1
   %4 = zext <16 x i1> %3 to <16 x i8>
@@ -148,8 +147,7 @@
 ; CHECK-NEXT:    movi v2.16b, #1
 ; CHECK-NEXT:    cmeq v0.16b, v0.16b, v1.16b
 ; CHECK-NEXT:    and v0.16b, v0.16b, v2.16b
-; CHECK-NEXT:    ushr v1.4s, v0.4s, #15
-; CHECK-NEXT:    orr v0.16b, v1.16b, v0.16b
+; CHECK-NEXT:    usra v0.4s, v0.4s, #15
 ; CHECK-NEXT:    ret
   %3 = icmp eq <16 x i8> %0, %1
   %4 = zext <16 x i1> %3 to <16 x i8>
@@ -167,8 +165,7 @@
 ; CHECK-NEXT:    movi v2.16b, #1
 ; CHECK-NEXT:    cmeq v0.16b, v0.16b, v1.16b
 ; CHECK-NEXT:    and v0.16b, v0.16b, v2.16b
-; CHECK-NEXT:    ushr v1.2d, v0.2d, #31
-; CHECK-NEXT:    orr v0.16b, v1.16b, v0.16b
+; CHECK-NEXT:    usra v0.2d, v0.2d, #31
 ; CHECK-NEXT:    ret
   %3 = icmp eq <16 x i8> %0, %1
   %4 = zext <16 x i1> %3 to <16 x i8>
Index: llvm/test/CodeGen/AArch64/fast-isel-cmp-vec.ll
===================================================================
--- llvm/test/CodeGen/AArch64/fast-isel-cmp-vec.ll
+++ llvm/test/CodeGen/AArch64/fast-isel-cmp-vec.ll
@@ -86,7 +86,6 @@
 ; CHECK-LABEL: icmp_constfold_v16i8:
 ; CHECK:       ; %bb.0:
 ; CHECK-NEXT:    movi.16b v0, #1
-; CHECK-NEXT:    and.16b v0, v0, v0
 ; CHECK-NEXT:    ret
   %1 = icmp eq <16 x i8> %a, %a
   br label %bb2
Index: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
===================================================================
--- llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -1972,6 +1972,12 @@
     Known = KnownBits::ashr(Known, Known2);
     break;
   }
+  case AArch64ISD::MOVI: {
+    ConstantSDNode *CN = cast<ConstantSDNode>(Op->getOperand(0));
+    Known =
+        KnownBits::makeConstant(APInt(Known.getBitWidth(), CN->getZExtValue()));
+    break;
+  }
   case AArch64ISD::LOADgot:
   case AArch64ISD::ADDlow: {
     if (!Subtarget->isTargetILP32())
@@ -23114,6 +23120,7 @@
 
 bool AArch64TargetLowering::isTargetCanonicalConstantNode(SDValue Op) const {
   return Op.getOpcode() == AArch64ISD::DUP ||
+         Op.getOpcode() == AArch64ISD::MOVI ||
          (Op.getOpcode() == ISD::EXTRACT_SUBVECTOR &&
           Op.getOperand(0).getOpcode() == AArch64ISD::DUP) ||
          TargetLowering::isTargetCanonicalConstantNode(Op);


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