[PATCH] D136148: [AMDGPU][NFC] Split MC tests into promoted from VOP2 to VOP3 and only VOP3

[Mirko Brkusanin via Phabricator via llvm-commits]

mbrkusanin marked 2 inline comments as done.
mbrkusanin added inline comments.


================
Comment at: llvm/test/MC/AMDGPU/gfx11_asm_vop3.s:9636
 
-v_xor_b32_e64 v5, v1, v2
-// GFX11: encoding: [0x05,0x00,0x1d,0xd5,0x01,0x05,0x02,0x00]
-
-v_xor_b32_e64 v5, v255, v255
-// GFX11: encoding: [0x05,0x00,0x1d,0xd5,0xff,0xff,0x03,0x00]
-
-v_xor_b32_e64 v5, s1, s2
-// GFX11: encoding: [0x05,0x00,0x1d,0xd5,0x01,0x04,0x00,0x00]
-
-v_xor_b32_e64 v5, s105, s105
-// GFX11: encoding: [0x05,0x00,0x1d,0xd5,0x69,0xd2,0x00,0x00]
-
-v_xor_b32_e64 v5, vcc_lo, ttmp15
-// GFX11: encoding: [0x05,0x00,0x1d,0xd5,0x6a,0xf6,0x00,0x00]
-
-v_xor_b32_e64 v5, vcc_hi, 0xaf123456
-// GFX11: encoding: [0x05,0x00,0x1d,0xd5,0x6b,0xfe,0x01,0x00,0x56,0x34,0x12,0xaf]
-
-v_xor_b32_e64 v5, ttmp15, src_scc
-// GFX11: encoding: [0x05,0x00,0x1d,0xd5,0x7b,0xfa,0x01,0x00]
-
-v_xor_b32_e64 v5, m0, 0.5
-// GFX11: encoding: [0x05,0x00,0x1d,0xd5,0x7d,0xe0,0x01,0x00]
-
-v_xor_b32_e64 v5, exec_lo, -1
-// GFX11: encoding: [0x05,0x00,0x1d,0xd5,0x7e,0x82,0x01,0x00]
-
-v_xor_b32_e64 v5, exec_hi, null
-// GFX11: encoding: [0x05,0x00,0x1d,0xd5,0x7f,0xf8,0x00,0x00]
-
-v_xor_b32_e64 v5, null, exec_lo
-// GFX11: encoding: [0x05,0x00,0x1d,0xd5,0x7c,0xfc,0x00,0x00]
-
-v_xor_b32_e64 v5, -1, exec_hi
-// GFX11: encoding: [0x05,0x00,0x1d,0xd5,0xc1,0xfe,0x00,0x00]
-
-v_xor_b32_e64 v5, 0.5, m0
-// GFX11: encoding: [0x05,0x00,0x1d,0xd5,0xf0,0xfa,0x00,0x00]
-
-v_xor_b32_e64 v5, src_scc, vcc_lo
-// GFX11: encoding: [0x05,0x00,0x1d,0xd5,0xfd,0xd4,0x00,0x00]
-
 v_xor_b32_e64 v255, 0xaf123456, vcc_hi
----------------
dp wrote:
> This test was broken, it was not moved to the intended destination file. Could you double-check that the number of tests (and test lines) is identical before and after the splitting?
Good catch. My script did not work properly for the last instruction in file.


================
Comment at: llvm/test/MC/AMDGPU/gfx11_asm_vop3_from_vop2.s:805
+
+v_lshlrev_b64 v[5:6], v1, vcc
+// GFX11: encoding: [0x05,0x00,0x3c,0xd7,0x01,0xd5,0x00,0x00]
----------------
dp wrote:
> This is a native VOP3 instruction; it should not be moved. Disassembler tests should be corrected as well.
Moved.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D136148/new/

https://reviews.llvm.org/D136148