[PATCH] D135324: [AArch64-SVE]: force using SVE in streaming mode to lower arithmetic and logical fixed-width vector ops.

[Hassnaa Hamdi via Phabricator via llvm-commits]

hassnaa-arm added a comment.

In D135324#3898875 <https://reviews.llvm.org/D135324#3898875>, @david-arm wrote:

> Hi @hassnaa-arm, I think this patch is very close to being ready! However, do you know why the test file sve-streaming-fixed-length-int-shifts.ll was deleted?

It was a fault while rebasing the parent patch to this patch.
In the parent patch, that deleted file was replaced by sve-streaming-mode-fixed-length-int-shifts.ll



================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:1396
       for (MVT VT : {MVT::v8i8, MVT::v16i8, MVT::v4i16, MVT::v8i16, MVT::v2i32,
-                     MVT::v4i32, MVT::v2i64})
+                     MVT::v4i32, MVT::v1i64, MVT::v2i64})
         addTypeForStreamingSVE(VT);
----------------
david-arm wrote:
> I remember in one of your previous patches that @sdesmalen mentioned you shouldn't need to add `v1i64` as it should be treated as a scalar. What happens if you remove it? I imagine your v1i64 tests might just generate scalar code?
Yes, at that patch, there were no tests needing custom-lowering for v1i64.

But in this patch, the test file of sve-streaming-mode-fixed-length-int-log.ll 
has invalid instructions for the test cases of : 
```
define <1 x i64> @and_v1i64(<1 x i64> %op1, <1 x i64> %op2)
```
```
define <1 x i64> @xor_v1i64(<1 x i64> %op1, <1 x i64> %op2)
```



Repository:
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  https://reviews.llvm.org/D135324/new/

https://reviews.llvm.org/D135324