[PATCH] D135324: [AArch64-SVE]: force using SVE in streaming mode to lower arithmetic and logical fixed-width vector ops.
David Sherwood via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Nov 1 06:23:58 PDT 2022
david-arm added a comment.
Hi @hassnaa-arm, I think this patch is very close to being ready! However, do you know why the test file sve-streaming-fixed-length-int-shifts.ll was deleted?
================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:1396
for (MVT VT : {MVT::v8i8, MVT::v16i8, MVT::v4i16, MVT::v8i16, MVT::v2i32,
- MVT::v4i32, MVT::v2i64})
+ MVT::v4i32, MVT::v1i64, MVT::v2i64})
addTypeForStreamingSVE(VT);
----------------
I remember in one of your previous patches that @sdesmalen mentioned you shouldn't need to add `v1i64` as it should be treated as a scalar. What happens if you remove it? I imagine your v1i64 tests might just generate scalar code?
Repository:
rG LLVM Github Monorepo
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https://reviews.llvm.org/D135324/new/
https://reviews.llvm.org/D135324
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