[PATCH] D130919: [MRI] isConstantPhysReg should also check if the register is clobbered by a RegMask

Tue Nov 1 04:51:00 PDT 2022

foad added inline comments.

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Comment at: llvm/lib/CodeGen/MachineCSE.cpp:280
   const MachineRegisterInfo &MRI = MF.getRegInfo();
-  return TRI.isCallerPreservedPhysReg(Reg, MF) ||
+  return TRI.isCallerPreservedPhysReg(Reg, MF) || TII.isIgnorableUse(MO) ||
          (MRI.reservedRegsFrozen() && MRI.isConstantPhysReg(Reg));
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Can you please split this part out into a separate patch for review? It causes significant codegen changes for AMDGPU and we need to be sure that the changes are OK.

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Comment at: llvm/test/CodeGen/AMDGPU/GlobalISel/udiv.i64.ll:1
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -global-isel -amdgpu-codegenprepare-disable-idiv-expansion=1 -mtriple=amdgcn-amd-amdpal -denormal-fp-math-f32=preserve-sign -mattr=+mad-mac-f32-insts < %s | FileCheck -check-prefixes=CHECK,GISEL %s
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I don't understant why these diffs are included in the patch. Can you double check? I don't think your patch affects codegen for any of:
```
  LLVM :: CodeGen/AMDGPU/GlobalISel/udiv.i64.ll
  LLVM :: CodeGen/AMDGPU/GlobalISel/urem.i64.ll
  LLVM :: CodeGen/AMDGPU/sgpr-control-flow.ll
```

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D130919/new/

https://reviews.llvm.org/D130919